ipd03n03lbg Infineon Technologies Corporation, ipd03n03lbg Datasheet
ipd03n03lbg
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ipd03n03lbg Summary of contents
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Type OptiMOS ® 2 Power-Transistor Package Marking • Qualified according to JEDEC • N-channel, logic level • Excellent gate charge x R DS(on) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Type IPD03N03LB ...
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Parameter Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB Electrical characteristics Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate-source leakage current Drain-source on-state resistance Gate resistance Transconductance 1) ...
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Parameter Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total ...
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Power dissipation P =f(T ) tot C 120 100 Safe operating area I =f =25 ° parameter 1000 limited by on-state ...
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Typ. output characteristics I =f =25 ° parameter 200 4 180 160 140 120 100 Typ. transfer characteristics I =f(V ...
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Drain-source on-state resistance =10 V DS(on -60 - Typ. capacitances C =f ...
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Avalanche characteristics =25 Ω parameter: T j(start) 100 150 ° Drain-source breakdown voltage V =f BR(DSS ...
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Package Outline PG-TO252-3-11: Outline Rev. 1.7 IPD03N03LB G PG-TO252-3-11 page 8 IPS03N03LB G 2008-04-11 ...
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Package Outline Rev. 1.7 IPD03N03LB G PG-TO251-3-11 page 9 IPS03N03LB G 2008-04-11 ...
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Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to ...