DM74ALS74AMX Fairchild Semiconductor, DM74ALS74AMX Datasheet

IC FLIP FLOP DUAL D POS 14SOIC

DM74ALS74AMX

Manufacturer Part Number
DM74ALS74AMX
Description
IC FLIP FLOP DUAL D POS 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74ALSr
Type
D-Typer
Datasheet

Specifications of DM74ALS74AMX

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
34MHz
Delay Time - Propagation
5ns
Trigger Type
Positive Edge
Current - Output High, Low
400µA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2000 Fairchild Semiconductor Corporation
Order Number
DM74ALS74AM
DM74ALS74ASJ
DM74ALS74AN
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clear and preset inputs, and also complementary Q
and Q outputs.
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Package Number Package Description
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006109
Features
Function Table
L
H
X
Q
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the V
0
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
Improved AC performance over LS74 at approximately
half the power
LOW State
Positive Edge Transition
Don't Care
HIGH State
PR
Previous Condition of Q
H
H
H
H
L
L
CLR
H
H
H
H
L
L
CC
Inputs
range
CLK
X
X
X
L
D
H
X
X
X
X
L
OH
September 1986
Revised February 2000
specification.
H (Note 1)
Q
Q
H
H
L
L
www.fairchildsemi.com
0
Outputs
H (Note 1)
Q
Q
H
H
L
L
0

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