74F74SJX Fairchild Semiconductor, 74F74SJX Datasheet

74F74SJX

Manufacturer Part Number

74F74SJX

Description

IC FLIP FLOP DUAL D POS 14SOP

Manufacturer

Fairchild Semiconductor

Series

74Fr

Type

D-Typer

Datasheets

1.74F74SJX.pdf (7 pages)

2.74F74SJX.pdf (7 pages)

Specifications of 74F74SJX

Function

Set(Preset) and Reset

Output Type

Differential

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

125MHz

Delay Time - Propagation

5.3ns

Trigger Type

Positive Edge

Current - Output High, Low

1mA, 20mA

Voltage - Supply

4.5 V ~ 5.5 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

14-SOIC (5.3mm Width), 14-SOP, 14-SOIJ

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

74F74SJX

Manufacturer:

SPT

Quantity:

Company:

Meier Automation Equipment Co., Limited

Part Number:

74F74SJX

Manufacturer:

FAIRCHI

Quantity:

20 000

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74F74SC

74F74SJ

74F74PC

74F74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The F74 is a dual D-type flip-flop with Direct Clear and Set

inputs and complementary (Q, Q) outputs. Information at

the input is transferred to the outputs on the positive edge

of the clock pulse. Clock triggering occurs at a voltage level

of the clock pulse and is not directly related to the transition

time of the positive-going pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Order Number

Package Number

IEEE/IEC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS009469

the outputs until the next rising edge of the Clock Pulse

input.

Asynchronous Inputs:

Connection Diagram

LOW input to S

LOW input to C

Clear and Set are independent of clock

Simultaneous LOW on C

makes both Q and Q HIGH

Package Description

sets Q to HIGH level

sets Q to LOW level

and S

April 1988

Revised September 2000

www.fairchildsemi.com

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