74F74SJ Fairchild Semiconductor, 74F74SJ Datasheet

IC FLIP FLOP DUAL D POS 14SOP

74F74SJ

Manufacturer Part Number
74F74SJ
Description
IC FLIP FLOP DUAL D POS 14SOP
Manufacturer
Fairchild Semiconductor
Series
74Fr
Type
D-Typer
Datasheet

Specifications of 74F74SJ

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
125MHz
Delay Time - Propagation
5.3ns
Trigger Type
Positive Edge
Current - Output High, Low
1mA, 20mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (5.3mm Width), 14-SOP, 14-SOIJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74F74SJ
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
74F74SJX
Manufacturer:
SPT
Quantity:
63
Part Number:
74F74SJX
Manufacturer:
FAIRCHI
Quantity:
20 000
Part Number:
74F74SJX
Manufacturer:
FAIRCHILD
Quantity:
6 947
© 1999 Fairchild Semiconductor Corporation
74F74SC
74F74SJ
74F74PC
74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q, Q) outputs. Information at
the input is transferred to the outputs on the positive edge
of the clock pulse. Clock triggering occurs at a voltage level
of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
IEEE/IEC
M14D
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009469
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
Connection Diagram
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
makes both Q and Q HIGH
Package Description
D
D
sets Q to HIGH level
sets Q to LOW level
D
and S
April 1988
Revised July 1999
D
www.fairchildsemi.com

Related parts for 74F74SJ

74F74SJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Unit Loading/Fan Out Pin Names Data Inputs Clock Pulse Inputs (Active Rising Edge Direct Clear Inputs (Active LOW Direct Set Inputs (Active ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL Propagation Delay PLH PHL ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14A Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

Related keywords