a25l016m-uf AMIC Technology Corporation, a25l016m-uf Datasheet
a25l016m-uf
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a25l016m-uf Summary of contents
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Preliminary Document Title 32Mbit / 16Mbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Revision History Rev. No. History 0.0 Initial issue PRELIMINARY (January, 2008, Version 0.0) A25L032/A25L016 Series 32Mbit / 16Mbit Low Voltage, Serial Flash Memory With ...
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Preliminary FEATURES Family of Serial Flash Memories - A25L032: 32M-bit /4M-byte - A25L016: 16M-bit /2M-byte Flexible Sector Architecture with 4KB sectors - Sector Erase (4K-bytes) in 0.4s (typical) - Block Erase (64K-bytes (typical) Page Program (up to 256 ...
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Block Diagram HOLD W Control Logic S C DIO DO Address register and Counter Pin Descriptions Pin No. Description C Serial Clock DIO Serial Data Input DO Serial Data Output Chip Select S Write Protect W Hold HOLD V Supply ...
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SIGNAL DESCRIPTION Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). The DO pin is also used as an input ...
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SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising ...
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OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program ...
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Write, Program and Erase instructions, as all instructions are ignored except one particular instruction Table 1. Protected Area Sizes A25L032 Status Register Content TB BP2 BP1 BP0 ...
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Hold Condition The Hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that ...
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A25L032 MEMORY ORGANIZATION The memory is organized as: 4,194,304 bytes (8 bits each) 64 blocks (64 Kbytes each) 1024 sectors (4 Kbytes each) 16,384 pages (256 bytes each) 64 OTP bytes located outside the main memory array Table 2. Memory ...
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Memory Organization (continued) Block Sector Address range 671 29F000h 41 656 290000h 655 28F000h 40 640 280000h 639 27F000h 39 624 270000h 623 26F000h 38 608 260000h 607 25F000h 37 592 250000h 591 24F000h 36 576 240000h 575 23F000h 35 ...
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Memory Organization (continued) Block Sector Address range 671 29F000h 41 656 290000h 655 28F000h 40 640 280000h 639 27F000h 39 624 270000h 623 26F000h 38 608 260000h 607 25F000h 37 592 250000h 591 24F000h 36 576 240000h 575 23F000h 35 ...
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Memory Organization (continued) Block Sector Address range 319 13F000h 19 304 130000h 303 12F000h 18 288 120000h 287 11F000h 17 272 110000h 271 10F000h 16 256 100000h 255 FF000h 15 240 F0000h 239 EF000h 14 224 E0000h 223 DF000h 13 ...
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A25L016 MEMORY ORGANIZATION The memory is organized as: 2,097,152 bytes (8 bits each) 32 blocks (64 Kbytes each) 512 sectors (4 Kbytes each) 8192 pages (256 bytes each) 64 OTP bytes located outside the main memory array Table 3. Memory ...
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Memory Organization (continued) Block Sector Address range 159 9F000h 9 144 90000h 143 8F000h 8 128 80000h 127 7F000h 7 112 70000h 111 6F000h 6 96 60000h 95 5F000h 5 80 50000h 79 4F000h 4 64 40000h PRELIMINARY (January, 2008, ...
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INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DIO) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S one-byte instruction ...
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Write Enable (WREN) The Write Enable (WREN) instruction (Figure 4.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
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Table 6. Protection Modes SRWD W Mode Bit Signal 1 0 Status Register is Writable (if the Software WREN instruction has set the 0 0 Protected WEL bit) The values in the (SPM) SRWD, TB, BP2, BP1, and BP0 bits ...
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Read Data Bytes (READ) The device is first selected by driving Chip Select ( The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of ...
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Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select ( The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the Fast_Read (0Bh) instruction except the data is output on two pins, DO and DIO, instead of just DO. This allows data to be transferred ...
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Read OTP (ROTP) The device is first selected by driving Chip Select ( The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on ...
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Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction ...
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Figure 13. How to permanently lock the 64 OTP bytes PRELIMINARY (January, 2008, Version 0.0) A25L032/A25L016 Series AMIC Technology Corp. 24 ...
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Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DIO and pin DO) instead of only one. Inputting ...
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Fast Read Dual Input-Output (BBh) The Fast Read Dual Input-Output (BBh) instruction is similar to the Fast_Read (0Bh) instruction except the data is input and output on two pins, DO and DIO, instead of just DO. This allows data to ...
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Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction ...
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Block Erase (BE) The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has ...
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Chip Erase (CE) The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device ...
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Read Device Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h. The device identification ...
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Read Electronic Manufacturer ID & Device ID (REMS) The Read Electronic Manufacturer ID & Device ID (REMS) instruction allows the 8-bit manufacturer identification code to be read, followed by one byte of device identification. The manufacturer identification is assigned by ...
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Release from Deep Power-down Electronic Signature (RES) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic instruction. Executing this instruction takes the device out of the Deep ...
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Figure 24. Release from Deep Power-down (RES) Instruction Sequence DIO High Impedance DO S Driving Chip Select ( ) High after the 8-bit instruction byte has been received by the device, but before the ...
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POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be S selected (that is Chip Select ( applied until V reaches the correct value (min) at Power-up, and then for a further ...
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Table 9. Power-Up Timing Symbol V V (minimum) CC(min (min) to device operation PU CC Note: These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set ...
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Absolute Maximum Ratings* Storage Temperature (TSTG -65 ° 150 ° C Lead Temperature during Soldering (Note 1) D.C. Voltage on Any Pin to Ground Potential . . ...
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Table 13. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 ...
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Figure 26. AC Measurement I/O Waveform 0.8V 0.2V PRELIMINARY (January, 2008, Version 0.0) Input Levels A25L032/A25L016 Series Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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Table 16. AC Characteristics Alt. Symbol f f Clock Frequency for the following instructions: FAST_READ PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR (2.7V~3.6V) / (3V~3.6V) f Clock Frequency for READ instructions ...
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Figure 27. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 28. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO PRELIMINARY (January, 2008, Version 0.0) tSLCH tCHDX MSB IN High Impedance ...
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Hold Timing Figure 29 DIO DO HOLD Figure 30. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO PRELIMINARY (January, 2008, Version 0.0) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 43 A25L032/A25L016 Series tHHCH tHHQX tCL LSB ...
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Part Numbering Scheme * Optional PRELIMINARY (January, 2008, Version 0.0) A25L032/A25L016 Series Package Material Blank: normal F: PB free Temperature* Package Type M = 209 mil SOP 150 mil SOP 8 Blank = DIP8 Device Version* Device ...
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... A25L032M-F A25L032M- for industrial operating temperature range: -40 ° +85 ° C Part No. Speed (MHz) (2.7V~3.6V) / (3.0V~3.6V) A25L016-F A25L016-UF 85/100 A25L016M-F A25L016M- for industrial operating temperature range: -40°C ~ +85°C PRELIMINARY (January, 2008, Version 0.0) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Active Read ...
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Package Information P-DIP 8L Outline Dimensions Notes: 1. Dimension D and E 2. Dimension B 3. Tolerance: ± 0.010” (0.25mm) unless otherwise specified. PRELIMINARY (January, 2008, Version 0.0) Dimensions in inches Symbol Min Nom Max 0.180 A ...
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Package Information SOP 8L (209mil) Outline Dimensions PRELIMINARY (January, 2008, Version 0. GAGE PLANE SEATING PLANE b Dimensions in mm Symbol Min Nom A 1.75 1.95 A 0.05 0. 1.70 1.80 2 ...