74F273SJX

Manufacturer Part Number74F273SJX
DescriptionIC FLIP FLOP OCTAL D 20SOP
ManufacturerFairchild Semiconductor
Series74F
TypeD-Type Bus
74F273SJX datasheet
 


Specifications of 74F273SJX

FunctionMaster ResetOutput TypeNon-Inverted
Number Of Elements1Number Of Bits Per Element8
Frequency - Clock160MHzDelay Time - Propagation7ns
Trigger TypePositive EdgeCurrent - Output High, Low1mA, 20mA
Voltage - Supply4.5 V ~ 5.5 VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Ordering Code:
Order Number
Package Number
74F273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
Features
Ideal buffer for MOS microprocessor or memory
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered, asynchronous Master Reset
See 74F377 for clock enable version
See 74F373 for transparent latch version
See 74F374 for 3-STATE version
Package Description
Connection Diagram
DS009511
April 1988
Revised August 1999
www.fairchildsemi.com

74F273SJX Summary of contents

  • Page 1

    ... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 1999 Fairchild Semiconductor Corporation Features Ideal buffer for MOS microprocessor or memory Eight edge-triggered D-type flip-flops ...

  • Page 2

    Unit Loading/Fan Out Pin Names D –D Data Inputs Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q –Q Data Outputs 0 7 Mode Select-Function Table Operating Mode Reset (Clear) Load “1” Load “0” ...

  • Page 3

    Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

  • Page 4

    AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t Clock to Output PHL t Propagation Delay PLH Output PHL AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or LOW ...

  • Page 5

    Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...

  • Page 6

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...