ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet
ds21ft40
Related parts for ds21ft40
ds21ft40 Summary of contents
Page 1
... The DS21FT40 MCM offers a high density packaging arrangement for the DS21Q44 E1 Enhanced Quad Framer. Three DS21Q44 silicon die are packaged in a Multi-Chip Module (MCM) with the electrical connections as shown in Figure 1-1. The DS21FT40 is closely related to the DS21FT44. Most of the functions of the DS21FT44 are available on the DS21FT40. The differences are listed in Table 1-1. ...
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... Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: FAS Frame Alignment Signal CAS Channel Associated Signaling MF Multiframe Si International bits CRC4 Cyclical Redundancy Check CCS Common Channel Signaling Sa Additional bits E-bit CRC4 Error Bits framer is totally independent from the receive side in both the clock DS21FT40 ...
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... DS21FT40 Schematic Figure 1 See Connecting Page DVSS DS21Q44 # 1 DVSS Signals Not Connected & Left Open Circuited Include: RLOS/LOTC TLINK0/1/2/3 RLINK RCLK1/2/3/4 TEST RLCLK MUX RPOS1/2/3/4 RCHBLK RNEG1/2/3/4 BTS RCHCLK RFSYNC FS0/FS1 RSER1/2/3/4 TLCLK RMSYNC1/2/3/4 WR* TCHCLK RD* RSYNC1/2/3/4 TCHBLK RSIG TSIG ...
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... DS21FT40 Schematic Figure 1-1 (continued) See Connecting Page Changes in DS21FT40 compared to DS21FT44 Table 1-1 1. The SYSCLK pins have been separated into TSYSCLK and RSYSCLK pins. 2. RMSYNC pins have been added. 3. FMS tied to Vdd. 4. The following signals are not available: RSIG / TSIG / 8MCLK / CLKSI / JTRST* / JTMS / JTCLK / JTDI / JTDO ...
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... DS21FT40 ENHANCED 12-Channel E1 FRAMER Figure 1-2 RPOS RCLK RNEG TPOS TNEG FRAMER #12 VDD Power VSS TEST C S* 64-Byte Buffer HDLC Engine DS0 Insertion Sa Extraction Timing Control Receive Side Framer data clock sync Transmit Side Formatter ...
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... HDLC CONTROLLER FOR THE SA BITS OR DS0............................................................................................. 55 14 .................................................................................................................................................. 55 ENERAL VERVIEW 14.2 HDLC S R TATUS EGISTERS 14 ASIC PERATION ETAILS 14.4 HDLC R D EGISTER ESCRIPTION 15. INTERLEAVED PCM BUS OPERATION .............................................................................................................. 64 16. TIMING DIAGRAMS................................................................................................................................................. 67 17. OPERATING PARAMETERS................................................................................................................................... 75 18. DS21FT40 MECHANICAL DIMENSIONS.............................................................................................................. 86 TABLE OF CONTENTS ......................................................................................................................................... 56 ........................................................................................................................................ 57 .................................................................................................................................. DS21FT40 ...
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... DOCUMENT REVISION HISTORY Revision 5-18-99 Initial Release 8-19-99 Concatenated DS21FT40 and DS21Q44 data sheets 8-26-99 Remove RCHBLK pins. 2-17-00 Corrected error in Figure 1-1 (removed RCHBLK pins). Notes DS21FT40 ...
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... DS21FT40 PIN DESCRIPTION Pin Description Sorted by Pin Number Table 2-1 Lead Symbols G20 A0 H20 A1 G19 A2 H19 A3 G18 A4 H18 A5 G17 A6 H17 A7 W15 BTS T8 CS1* Y4 CS2* Y15 CS3* L20 D0 M20 D1 L19 D2 M19 D3 L18 D4 M18 D5 L17 D6 M17 D7 C7 DVDD1 E4 DVDD1 D2 DVDD1 K3 DVDD2 U7 DVDD2 P2 DVDD2 V19 ...
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... Receive Positive Data for Framer 1. I Receive Positive Data for Framer 2. I Receive Positive Data for Framer 3. I Receive Positive Data for Framer 4. I Receive Positive Data for Framer 5. I Receive Positive Data for Framer 6. I Receive Positive Data for Framer DS21FT40 ...
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... Receive System Clock for Framer 9. I Receive System Clock for Framer 10. I Receive System Clock for Framer 11. I Receive System Clock for Framer 12. I Transmit Clock for Framer 1. I Transmit Clock for Framer 2. I Transmit Clock for Framer 3. I Transmit Clock for Framer DS21FT40 ...
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... Transmit Serial Data for Framer 5. I Transmit Serial Data for Framer 6. I Transmit Serial Data for Framer 7. I Transmit Serial Data for Framer 8. I Transmit Serial Data for Framer 9. I Transmit Serial Data for Framer 10. I Transmit Serial Data for Framer 11 DS21FT40 ...
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... Transmit System Clock for Framer 9. I Transmit System Clock for Framer 10. I Transmit System Clock for Framer 11. I Transmit System Clock for Framer 12. I Write Input. – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect DS21FT40 ...
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... No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect DS21FT40 ...
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... No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect – No Connect DS21FT40 ...
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... DS21FT40 PCB Land Pattern Figure 2-1 The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed through the MCM from the top rpos rclk ts tsync tclk sync1 4 4 rsync ...
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... Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. TCLK Transmit Clock Input TSER Transmit Serial Data Input TSYSCLK Transmit System Clock Input TSYNC Transmit Sync Input /Output TSSYNC Transmit System Sync Input TPOS Transmit Positive Data Output Output TNEG Transmit Negative Data Output Output DS21FT40 ...
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... RCLK Receive Clock Input Input RSER Receive Serial Data Output RSYNC Receive Sync Input /Output RMSYNC Receive Multiframe Sync Output RSYSCLK Receive System Clock Input RPOS Receive Positive Data Input Input RNEG Receive Negative Data Input Input DS21FT40 ...
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... AD0 TO AD7 Data Bus or Address/Data Bus Input /Output A0 TO A5, A7 Address Bus Input ALE (AS Address Latch Enable (Address Strobe Input BTS Bus Type Select Input RD* (DS) Read Input (Data Strobe) Input FS0 AND FS1 Framer Selects Input DS21FT40 ...
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... Useful in board level testing. SUPPLY PINS Signal Name: Signal Description: Signal Type: 2.97 to 3.63 volts. Signal Name: Signal Description: Signal Type: 0.0 volts. 3. DS21FT40 REGISTER MAP Register Map for Each Quad Framer Sorted by Address Table 3-1 ADDRESS R BPV or Code Violation Count BPV or Code Violation Count 2 ...
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... DS21FT40 – write to 00H.) 23 R/W Transmit Channel Blocking 2 (Not applicable to DS21FT40 – write to 00H.) 24 R/W Transmit Channel Blocking 3 (Not applicable to DS21FT40 – write to 00H.) 25 R/W Transmit Channel Blocking 4 (Not applicable to DS21FT40 – write to 00H.) 26 R/W Transmit Idle 1 27 R/W Transmit Idle 2 28 R/W Transmit Idle 3 29 R/W Transmit Idle 4 2A ...
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... Receive Si bits Align Frame 59 R Receive Si bits Non-Align Frame 5A R Receive Remote Alarm Bits 5B R Receive Sa4 Bits 5C R Receive Sa5 Bits REGISTER NAME DS21FT40 REGISTER ABBREVIATION RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 ...
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... R/W Receive Channel 4 84 R/W Receive Channel 5 85 R/W Receive Channel 6 86 R/W Receive Channel 7 87 R/W Receive Channel 8 88 R/W Receive Channel 9 REGISTER NAME DS21FT40 REGISTER ABBREVIATION RSa6 RSa7 RSa8 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 ...
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... Not used B0 R/W HDLC Control Register B1 R/W HDLC Status Register B2 R/W HDLC Interrupt Mask Register B3 R/W Receive HDLC Information Register B4 R/W Receive HDLC FIFO Register REGISTER NAME DS21FT40 REGISTER ABBREVIATION RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 ...
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... Register banks CxH, DxH, ExH, and FxH are not accessible. 4. PARALLEL PORT The DS21FT40 is controlled via either a non–multiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21FT40 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected ...
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... Power–Up Sequence The DS21FT40 does not automatically clear its register space on power–up. After the supplies are stable, each of the four framer’s register space should be configured for operation by writing to all of the internal registers. This includes setting the Test and all unused registers to 00Hex. ...
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... NAME AND DESCRIPTION Sa8 Bit Select. Not applicable for DS21FT40. Sa7 Bit Select. Not applicable for DS21FT40. Sa6 Bit Select. Not applicable for DS21FT40. Sa5 Bit Select. Not applicable for DS21FT40. Sa4 Bit Select. Not applicable for DS21FT40 DS21FT40 ITU SPEC. G.706 4 ...
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... TSYNC Mode Select frame mode (see the timing in Section 16 CAS and CRC4 multiframe mode (see the timing in Section 16) TSYNC I/O Select TSYNC is an input 1 = TSYNC is an output DS21FT40 (LSB) TSA1 TSM TSIO ...
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... TPOSO and TNEGO are 1/2 TCLKO period wide Automatic E–Bit Enable E–bits not automatically set in the transmit direction 1 = E–bits automatically set in the transmit direction Function of RLOS/LOTC Pin. Not applicable for DS21FT40. Should be cleared to zero. TCRC4 RSM NAME AND DESCRIPTION Framer Loopback. 0=loopback disabled 1=loopback enabled Transmit HDB3 Enable ...
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... RSERC CCR2.3 LOTCMC CCR2.2 RFF CCR2.1 NAME AND DESCRIPTION Receive G.802 Enable. See Section 16 for details. Not applicable for DS21FT40. Should be cleared to zero. Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled ARA RSERC LOTCMC NAME AND DESCRIPTION Error Counter Update Select. See Section 7 for details. ...
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... CCR2.0 AUTOMATIC ALARM GENERATION The DS21FT40 can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception, or loss of receive carrier (or signal) ...
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... RSER pin 1=re–insert the signaling bits into data stream presented at the RSER pin Transmit Side Hardware Signaling Insertion Enable. Not applicable for DS21FT40. Should be cleared to zero. Transmit Side Backplane Clock Select. 0=if TSYSCLK is 1.544 MHz 1=if TSYSCLK is 2.048 MHz Receive Carrier Loss (RCL) Alternate Criteria. ...
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... Not Assigned. Should be set to zero when written Not Assigned. Should be set to zero when written Not Assigned. Should be set to zero when written Not Assigned. Should be set to zero when written Not Assigned. Should be set to zero when written (LSB) RCM2 RCM1 RCM0 (LSB) TCLKSRC RESR TESR DS21FT40 ...
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... The specific details on the four registers pertaining to the HDLC controller are covered in Section 14 but they operate the same as the other status registers in the DS21FT40 and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one ...
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... Interrupt request pending. FRAMER 1 HDLC CONTROLLER INTERRUPT REQUEST interrupt request pending Interrupt request pending. FRAMER 1 SR1 or SR2 INTERRUPT REQUEST interrupt request pending Interrupt request pending. FRAMER 0 HDLC CONTROLLER INTERRUPT REQUEST interrupt request pending DS21FT40 (LSB) F0HDLC F0SR ...
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... FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word DS21FT40 (LSB) CRCRC FASRC CASRC (LSB) FASSA ...
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... Receive Remote Alarm. Set when a remote alarm is received at RPOS and RNEG. Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1) consecutive zeros have been detected at RPOS and RNEG. Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream DS21FT40 (LSB) RCL RLOS ...
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... Transmit Align Frame. Set every 250 s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated CLEAR CRITERIA G.775 / G.962 LOTC RCMF DS21FT40 ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1 ...
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... Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All Ones. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled DS21FT40 (LSB) RCL RLOS ...
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... One Second Timer. 0=interrupt masked 1=interrupt enabled Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Transmit Side Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled DS21FT40 (LSB) RCMF TSLIP ...
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... LSB of the 10–bit code violation count (note 1) (note 1) (note 1) CRC4 CRC3 CRC2 NAME AND DESCRIPTION MSB of the 10–Bit CRC4 error count LSB of the 10–Bit CRC4 error count (LSB VCR1 V1 V0 VCR2 (LSB) CRC9 CRC8 CRC1 CRC0 DS21FT40 CRCCR1 CRCCR2 ...
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... The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter. 8. DS0 MONITORING FUNCTION Each framer in the DS21FT40 has the ability to monitor one DS0 64Kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register ...
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... Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted DS21FT40 (LSB) TCM2 TCM1 TCM0 (LSB ...
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... Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 8 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode DS21FT40 (LSB) RCM1 RCM0 ...
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... RDS0M.0 9. SIGNALING OPERATION Each framer in the DS21FT40 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 9 ...
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... D(8) A(23) B(23) D(9) A(24) B(24) D(10) A(25) B(25) D(11) A(26) B(26) D(12) A(27) B(27) D(13) A(28) B(28) D(14) A(29) B(29) D(15) A(30) B(30) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30. Their validity should be qualified by checking for DS21FT40 (LSB RS1 (30) C(16) D(16) RS2 (31) C(17) D(17) RS3 (32) C(18) D(18) RS3 (33) C(19) D(19) RS5 (34) C(20) D(20) RS6 (35) C(21) D(21) RS7 (36) B(22) B(22) RS8 (37) C(23) D(23) RS9 (38) C(24) D(24) RS10 (39) ...
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... B(17) D(3) A(18) B(18) D(4) A(19) B(19) D(5) A(20) B(20) D(6) A(21) B(21) B(7) B(22) B(22) D(8) A(23) B(23) D(9) A(24) B(24) D(10) A(25) B(25) D(11) A(26) B(26) D(12) A(27) B(27) D(13) A(28) B(28) D(14) A(29) B(29) D(15) A(30) B(30) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30 DS21FT40 (LSB TS1 (40) C(16) D(16) TS2 (41) C(17) D(17) TS3 (42) C(18) D(18) TS4 (43) C(19) D(19) TS5 (44) C(20) D(20) TS6 (45) C(21) D(21) TS7 (46) B(22) B(22) TS8 (47) C(23) D(23) TS9 (48) C(24) D(24) TS10 (49) C(25) D(25) TS11 (4A) C(26) D(26) TS12 (4B) C(27) D(27) TS13 (4C) C(28) D(28) TS14 (4D) C(29) D(29) TS15 (4E) ...
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... PER–CHANNEL CODE GENERATION AND LOOPBACK Each framer in the DS21FT40 can replace data on a channel–by–channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The receive direction is from the E1 line to the backplane and is covered in Section 10.2. ...
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... Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel TIDR4 TIDR3 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last DS21FT40 (LSB) CH2 CH1 TIR1 (26) CH10 CH9 TIR2 (27) ...
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... TC register into the transmit data stream NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane DS21FT40 (LSB TC1 (60) (LSB) CH2 CH1 TCC1 (A0) ...
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... ELASTIC STORES OPERATION Each framer in the DS21FT40 contains dual two–frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1 rate ...
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... ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION Each framer in the DS21FT40 provides for access to both the Sa and the Si bits via two different methods. The first method involves using the internal RAF/RNAF and TAF/TNAF registers and is discussed in Section 13.1. The second method, which is covered in Section 13.2, involves an expanded version of the first method. 13.1 INTERNAL REGISTER SCHEME BASED ON DOUBLE– ...
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... Frame Alignment Signal Bit Frame Alignment Signal Bit. A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non–Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit DS21FT40 (LSB (LSB) Sa6 Sa7 Sa8 ...
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... TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB [Must be programmed with the 7 bit FAS word; the DS21FT40 does not automatically set these bits] SYMBOLS POSITION Si TAF.7 0 TAF.6 0 TAF.5 1 TAF.4 1 TAF.3 0 TAF.2 1 TAF.1 1 TAF.0 TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex) ...
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... TRA register into the transmit data stream. Additional Bit 4 Insertion Control Bit. 0=do not insert data from the TSa4 register into the transmit data stream. 1=insert data from the TSa4 register into the transmit data stream FUNCTION (LSB) Sa6 Sa7 DS21FT40 Sa8 ...
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... TSaCR.0 14. HDLC CONTROLLER FOR THE SA BITS OR DS0 Each framer in the DS21FT40 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this operation is covered in Section 14.1. 14.1 GENERAL OVERVIEW Each framer contains a complete HDLC controller with 64– ...
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... HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels status information on transmit HDLC controller enables/disables transmission of BOC codes access to 64–byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels DS21FT40 ...
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... This operation is key in controlling the DS21FT40 with higher–order software languages. Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin ...
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... FIFO at THFR. The HDLC controller will clear this bit when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable enable the zero stuffer (normal operation disable the zero stuffer. Transmit CRC Defeat enable CRC generation (normal operation disable CRC generation DS21FT40 (LSB) TZSD TCRCD ...
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... THIR register for details. RHALF RNE THALF NAME AND DESCRIPTION Not Assigned. Should be set to zero. Receive Packet End interrupt masked interrupt enabled. Receive Packet Start interrupt masked interrupt enabled DS21FT40 (LSB) TNF TMEND (LSB) TNF TMEND ...
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... Closing Byte. Set when the byte available for reading in the receive FIFO at RFDL is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RHFR is the first byte of a message DS21FT40 (LSB) CBYTE OBYTE ...
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... Transmit FIFO Empty. A real–time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real–time bit that is set high when the FIFO is full. Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent DS21FT40 (LSB) HDLC2 HDLC1 HDLC0 (LSB) EMPTY ...
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... This option is not applicable for the DS21FT40. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select DS21FT40 (LSB) HDLC1 HDLC0 (LSB) RD1 RD0 ...
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... Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8 route DS0 channels from the HDLC controller. TDC1.5 is used to determine how the DS0 channels are selected. DS0 Selection Mode. Not applicable for the DS21FT40. Should be cleared to zero DS21FT40 (LSB) RDB2 ...
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... In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21FT40 can be configured to allow each framer’s data and signaling busses to be multiplexed into higher speed data and signaling busses eliminating external hardware saving board space and cost ...
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... Master Device Bus Select Bit 0 See table 15-1. Master Device Bus Select Bit 1 See table 15-1. Slave device. Master device with 1 slave device (4.096 MHz bus rate) Master device with 3 slave devices (8.192 MHz bus rate) Reserved (LSB) INTSEL MSEL0 MSEL1 Function DS21FT40 ...
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... TSYSCLK3 RSYNC2 TSSYNC2 RSER2 TSER2 SYSCLK SYNC INPUT RSER TSER Bus 2 FRAMER 2 FRAMER 3 RSYSCLK2 RSYSCLK3 TSYSCLK2 TSYSCLK3 RSYNC2 RSYNC3 TSSYNC2 TSSYNC3 RSER2 RSER3 TSER2 TSER3 DS21FT40 RSYNC3 TSSYNC3 RSER3 TSER3 SYSCLK SYNC INPUT RSER TSER SYSCLK SYNC INPUT RSER TSER ...
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... There RCLK delay from RPOS, RNEG to RSER 2. Shown is a non-align frame boundary CHANNEL 1 CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 1 LSB Sa4 Sa5 Sa6 Sa7 Sa8 LSB CHANNEL 2 MSB DS21FT40 ...
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... RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) Figure 16-4 RSYSCLK CHANNEL 31 RSER 1 RSYNC 2 RSYNC Notes: 1. RSYNC is in the output mode (RCR1 RSYNC is in the input mode (RCR1 CHANNEL 24/32 LSB CHANNEL 32 LSB LSB MSB CHANNEL 1/2 MSB F CHANNEL 1 MSB DS21FT40 ...
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... FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 BIT DETAIL FRAMER 0, CHANNEL 1 LSB MSB FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FRAMER 1, CHANNEL 1 LSB FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FRAMER 0, CHANNEL 2 LSB DS21FT40 ...
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... TSYNC is in the output mode (TCR1 Shown is a non-align frame boundary CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB A CHANNEL 1 A Sa4 Sa5 Sa6 LSB CHANNEL 2 LSB MSB Sa7 Sa8 MSB DS21FT40 ...
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... TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) Figure 16-9 TSYSCLK CHANNEL 23 TSER TSSYNC Notes: 1. The F-bit position is ignored by the DS21FT40 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) Figure 16-10 TSYSCLK CHANNEL 31 TSER TSSYNC CHANNEL 24 LSB MSB LSB ...
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... FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 BIT DETAIL FRAMER 0, CHANNEL 1 MSB MSB LSB FR1 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FRAMER 1, CHANNEL 1 LSB FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FRAMER 0, CHANNEL 2 LSB DS21FT40 ...
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... DS21FT40 FRAMER SYNCHRONIZATION FLOWCHART Figure 16-13 RLOS = 1 Resync if RCR1 Increment CRC4 Sync Counter; CRC4SA = 0 Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) 8ms CRC4 Multiframe Search Time (if enabled via CCR1.0) Out CRC4SA = 1 CRC4 Sync Criteria Met ...
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... DS21FT40 TRANSMIT DATA FLOW Figure 16- GIN E TNAF.0 Data Source DS0 Data MUX Source MUX (TDC1) (TDC1/2) TAF TNAF.5 TAF/TNAF Bit MUX 0 Timeslot 0 Pass-Through (TCR1. Bit Insertion CRC4 Multiframe Alignment Word Generation (CCR.4) KEY: = Register = Device Pin ...
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... –1 +4 (0ºC to 70ºC for DS21FT40; 0ºC to +85ºC for DS21FT40N) MAX UNITS 5.5 V +0.8 V 3.63 V MAX UNITS 2.97 to 3.63V for DS21FT40 2.97 to 3.63V for DS21Q44N) MAX UNITS mA +1.0 µA 1.0 µ DS21FT40 NOTES (t =25ºC) A NOTES NOTES ...
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... F 10 RWH 50 RWS DHR 0 DHW t 15 ASL t 10 AHL t 20 ASD 30 ASH 10 ASED 20 DDR 50 DSW 2.97 to 3.63V for DS21FT40 DD = 2.97 to 3.63V for DS21FT40N) MAX UNITS DS21FT40 NOTES ...
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... V DD –40ºC to +85º MIN TYP 2.97 to 3.63V for DS21FT40; = 2.97 to 3.63V for DS21FT40N) MAX UNITS DS21FT40 NOTES ...
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... Valid Delay RCLK to RSYNC Delay RSYSCLK to RSER Valid Delay RSYSCLK to RMSYNC, RSYNC See Figures 17-8 to 17-10 for details. NOTES: 1. RSYSCLK = 1.544 MHz. 2. RSYSCLK = 2.048 MHz. (0ºC to 70º –40ºC to +85º 2.97 to 3.63V for DS21FT40N) DD MIN TYP t 488 ...
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... SP t 122 448 2.97 to 3.63V for DS21FT40; = 2.97 to 3.63V for DS21FT40N) MAX UNITS – – DS21FT40 NOTES 1 2 ...
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... CS* t ASL AD0-AD7 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 17-2 ALE PW t ASD RD* t ASD WR CS* t ASL AD0-AD7 t CYC ASH t ASED DDR t AHL t CYC ASH t ASED AHL DHR DHW t DSW DS21FT40 ...
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... INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 17 Address Valid WR* t1 0ns min. CS* 0ns min. RD* ASH t ASED t CYC t RWS t DDR t CS AHL t DSW Data Valid 5ns min. / 20ns max 75ns max RWH t DHR DHW t5 t4 0ns min. DS21FT40 ...
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... MOTOROLA BUS READ AC TIMING (BTS = 1 / MUX = 0) Figure 16. Address Valid R/W* t1 0ns min. CS* 0ns min 10ns min 75ns min. Data Valid 5ns min. / 20ns max 75ns max 10ns min. t4 0ns min 0ns min. DS21FT40 ...
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... R/W* t1 0ns min. CS* 0ns min. DS* RECEIVE SIDE AC TIMING Figure 17-8 RCLK RMSYNC Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 10ns t7 min 75ns min. MSB of Channel 10ns t8 min. t4 0ns min. DS21FT40 ...
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... RSYNC is in the output mode (RCR1 RSYNC is in the input mode (RCR1 RECEIVE LINE INTERFACE AC TIMING Figure 17- MSB of Channel DS21FT40 ...
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... TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 17- TCLK TPOS, TNEG DS21FT40 ...
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... DS21FT40 MECHANICAL DIMENSIONS DS21FT40 ...
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... Figure 18-1 uses standard capacitors, two .47 uf ceramics and two .01uf ceramics. Since VDD and VSS signals will typically pass vertically to the power and ground planes of a PCB, the de-coupling caps must be placed as close to the DS21FT40 as possible and routed vertically to power and ground planes. ...