ds2165 Maxim Integrated Products, Inc., ds2165 Datasheet - Page 3

• Manufacturer Part Number: ds2165
• Description: Ds2165, Ds2165q 16/24/32kbps Adpcm Processor
• Manufacturer: Maxim Integrated Products, Inc.

CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN
10
11
12
13
14
16
17
18
20
21
22
23
24
25
26
27
28
2
3
4
6
7
8
9
SYMBOL
MCLK
CLKX
XOUT
YOUT
CLKY
SCLK
VDD
TM0
TM1
VSS
FSX
FSY
RST
SPS
XIN
YIN
SDI
A0
A1
A2
A3
A4
A5
CS
TYPE
—
—
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Reset. A high-low-high transition resets the algorithm. The device should be
reset on power-up and when changing to or from the hardware mode.
Test Modes 0 and 1. Connect to V
Address Select. A0 = LSB, A5 = MSB. Must match address/command word
to enable the serial port.
Serial Port Select. Connect to V
select the hardware mode.
Master Clock. 10MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
Signal Ground. 0V
X Data In. Sampled on falling edge of CLKX during selected time slots.
X Data Clock. Data clock for the X-side PCM interface; must be
synchronous with FSX.
X Frame Sync. 8kHz frame sync for the X-side PCM interface.
X Data Output. Updated on rising edge of CLKX during selected time slots.
Serial Data Clock. Used to write to the serial port registers.
Serial Data In. Data for on-board control registers; sampled on the rising
edge of SCLK. LSB sent first.
Chip Select. Must be low to write to the serial port.
Y Data Output. Updated on rising edge of CLKY during selected time slots.
Y Frame Sync. 8kHz frame sync for the Y-side PCM interface.
Y Data Clock. Data clock for the Y-side PCM interface; must be
synchronous with FSY.
Y Data In. Sampled on falling edge of CLKY during selected time slots.
Positive Supply. 5.0V (3.0V for DS2165QL)
3 of 17
FUNCTION
DD
SS
to select the serial port; connect to V
for normal operation.
DS2165Q
SS
to