ds21372 Maxim Integrated Products, Inc., ds21372 Datasheet
ds21372
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ds21372 Summary of contents
Page 1
... Two categories of test pattern generation (Pseudo-random and Repetitive) conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates ranging from MHz. This wide range of operating frequency allows the DS21372 to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, Routers, Bridges, CSUs, DSUs, and CPE equipment ...
Page 2
... TDATA pin. 1.2 PATTERN SYNCHRONIZATION The DS21372 expects to receive the same pattern that it transmitted. The synchronizer examines the data at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard synchronizer with the Sync Enable and Resync bits in the Pattern Control Register. ...
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... POWER-UP SEQUENCE On power-up, the registers in the DS21372 will random state. The user must program all the internal registers to a known state before proper operation can be insured. DS21372 FUNCTIONAL BLOCK DIAGRAM Figure 1 DS21372 PATTERN GENERATION BLOCK DIAGRAM Figure 2 NOTES: 1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern. ...
Page 4
... BCR and BECR registers and clears the internal count registers logically OR’ed with control bit PCR.4. Should be tied not used. SS Receive Loss Of Sync. Indicates the real time status of the receive synchronizer. Active high output DS21372 , ADx, TDATA, RLOS). INT (DS), RD ...
Page 5
... R Bit Counter Register 0. NOTE: 1. The Test Register must be set to 00 hex to insure proper operation of the DS21372. Receive Load. A positive-going edge loads the previous 32 bits of data received at RDATA into the Pattern Receive Registers logically OR’ed with control bit PCR.3. Should be tied to V Receive Data ...
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... Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS21372 latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during ...
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... PTR.1 PT0 PTR.0 6. PATTERN CONTROL REGISTER The Pattern Control Register (PCR) is used to configure the operating parameters of the DS21372 and to control the patterns being generated and received. Also the PCR is used to control the pattern synchronizer and the error and bit counters. - LB4 ...
Page 8
... Initiate Manual Resync Process. A low to high transition will force the DS21372 to resynchronize to the incoming pattern at RDATA. Must be cleared and set again for a subsequent resync. Transmit/Receive Loopback Select. When enabled, the RDATA input is disabled; TDATA continues to output data as normal ...
Page 9
... ERROR INSERT REGISTER The Error Insertion Register (EIR) controls circuitry within the DS21372 that allows the generated pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under microcontroller control) via the EIR.3 bit. ...
Page 10
... DS21372 PSR1 PSR0 TINV RINV ...
Page 11
... BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the BCR by either toggling the LC bit or pin. The DS21372 latches the bit count into the BCR registers and clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The bit count and bit error count (available via the BECRs) are used by an external processor to compute the BER performance on a loop or channel basis ...
Page 12
... The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the BECR by either toggling the LC bit or pin. The DS21372 latches the bit error count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input pin toggles from low to high ...
Page 13
... PR5 11. STATUS REGISTER AND INTERRUPT MASK REGISTER The Status Register (SR) contains information on the current real time status of the DS21372. When a particular event has occurred, the appropriate bit in the register will be set All of the bits in these registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a bit is set any of the registers, it will remain set until the user reads that bit ...
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... Receive Loss Of Sync interrupt masked 1 = interrupt enabled Bit Error Detection interrupt masked 1 = interrupt enabled Bit Counter Overflow interrupt masked 1 = interrupt enabled Bit Error Count Overflow interrupt masked 1 = interrupt enabled Sync interrupt masked 1 = interrupt enabled DS21372 (LSB) BCOF BECOF SYNC ...
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... AC TIMING AND DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21372N Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability ...
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... DHR t 0 DHW t 15 ASL t 10 AHL t 20 ASD PW 30 ASH ASED t 5 DDR t 50 DSW for DS21372; V =3.3V 10 for DS21372N; V =3.3V 10%) DD TYP MAX UNITS DS21372 ...
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... INTEL BUS READ AC TIMING (BTS=0) FIGURE 3 ALE PW t ASD WR t ASD AD0-AD7 t CYC ASH t ASED ASL DDR t AHL DHR DS21372 ...
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... INTEL BUS WRITE AC TIMING (BTS=0) FIGURE 4 ALE PW t ASD RD t ASD AD0-AD7 t CYC ASH t ASED ASL t DSW t AHL DHW DS21372 ...
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... MOTOROLA BUS AC TIMING (BTS=1) FIGURE ASD DS PW R/W AD0-AD7 (READ) CS AD0-AD7 (WRITE) ASH ASED EL t CYC t RWS t ASL t DDR t AHL ASL t DSW t AHL RWH t DHR DHW DS21372 ...
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... SU1 t 0 HD1 t 5 SU2 t 0 HD2 t 25 WRL for DS21372 - +85 C for DS21372N; V SYMBOL MIN TYP WTL t 5 STL t 0 HTL ...
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... TDIS is low about the rising edge of TCLK. TRANSMIT AC TIMING FOR THE TL INPUT Figure 8 NOTE: The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the new pattern (the shaded one) will appear after two TCLK periods DS21372 ...
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... DS21372 32-PIN TQFP DIM MIN MAX A - 1.20 A1 0.05 0.15 A2 0.95 1.05 D 8.80 9.20 D1 7.00 BSC E 8.80 9.20 E1 7.00 BSC L 0.45 0.75 e 0.80 BSC B 0.30 0.45 C 0.09 0. DS21372 ...