DM74ALS374WM Fairchild Semiconductor, DM74ALS374WM Datasheet

DM74ALS374WM

Manufacturer Part Number

DM74ALS374WM

Description

IC FLIP FLOP OCTAL D 3ST 20SOIC

Manufacturer

Fairchild Semiconductor

Series

74ALSr

Type

D-Type Busr

Datasheets

1.DM74ALS374WM.pdf (7 pages)

2.DM74ALS374WM.pdf (7 pages)

Specifications of DM74ALS374WM

Function

Standard

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

35MHz

Delay Time - Propagation

3ns

Trigger Type

Positive Edge

Current - Output High, Low

2.6mA, 24mA

Voltage - Supply

4.5 V ~ 5.5 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Allchip Electronic(HK) Limited

Part Number:

DM74ALS374WMX

Manufacturer:

Quantity:

16 736

Current page: 1 of 7
Download datasheet (76Kb)

DM74ALS374WM

DM74ALS374SJ

DM74ALS374N

DM74ALS374

Octal 3-STATE D-Type Edge-Triggered Flip-Flop

General Description

This 8-bit register features totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high-logic-level drive provides this register with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. It is particularly attractive for

implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

The eight flip-flops of the DM74ALS374 are edge-triggered

D-type flip-flops. On the positive transition of the clock, the

Q outputs will be set to the logic states that were set up at

the D inputs.

A buffered output control input can be used to place the

eight outputs in either a normal logic state (HIGH or LOW

logic levels) or a high-impedance state. In the high-imped-

ance state the outputs neither load nor drive the bus lines

significantly.

The output control does not affect the internal operation of

the flip-flops. That is, the old data can be retained or new

data can be entered even while the outputs are OFF.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package Number

M20B

M20D

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006113

Features

Switching specifications at 50 pF

Switching specifications guaranteed over full

temperature and V

Advanced oxide-isolated, ion-implanted Schottky TTL

process

Functionally and pin-for-pin compatible with LS TTL

counterpart

Improved AC performance over DM74LS374 at approxi-

mately half the power

3-STATE buffer-type outputs drive bus lines directly

Package Description

range

September 1986

Revised February 2000

www.fairchildsemi.com

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