ds1075 ETC-unknow, ds1075 Datasheet
ds1075
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ds1075 Summary of contents
Page 1
... Input/Output pin becomes the oscillator output. The DS1075 is available in 8–pin DIP or SOIC pack- ages, allowing the generation of a clock signal easily, economically and using minimal board area. 101697 1/16 ...
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... DS1075 BLOCK DIAGRAM Figure 1 PART NO. INTOSC SUFFIX FREQUENCY INTERNAL OSCILLATOR 100 MHz –100 –80 80 MHz –66 66 MHz –60 60 MHz M MSEL E/I EN0 DIV1 PDN POWER ON RESET SIGNAL PATH 101697 2/16 en OSCIN en INTOSC XTAL M rst sel INTCLK EXTCLK en sel OUT0 en en MCLK PROGRAMMABLE ...
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... OSCIN to provide an alternative frequency reference crystal is not used this pin should be left open. Output Enable Function (OE pin): The DS1075 also features a “synchronous” output enable. When high logic level the oscillator free runs. When this pin is taken low OUT is held low, immediately if OUT is already low it’ ...
Page 4
... DS1075 MUX WORD Figure 2 (MSB EN0 E/I This bit selects either the internal oscillator or the exter- nal/crystal reference. 1=External/Crystal Table 1 PDN PDN/SELX BIT E/I PIN DIV1 This bit allows the master clock to be routed directly to the output (DIV1=1) ...
Page 5
... Since the output enable, internal master oscillator and/or external master oscillator are likely all asynchro- nous there is the possibility of timing difficulties in the application. To minimize these difficulties the DS1075 features an “enabling sequencer” to produce predict- able results when the device is enabled and disabled. In particular the output gating is configured so that trun- cated output pulses can never be produced ...
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... DS1075 Disable Timing If OE goes low while OUT is high, the output will be dis- abled on the completion of the output pulse. If OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE and the rising edge of MCLK < t the result will be one addi- ...
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... PERIOD OF INTERNAL CLOCK PERIOD OF EXTERNAL CLOCK Elow Ehigh time interval between the falling edge of SELX and the first rising edge of the externally derived clock is t Ehigh Approximate maximum and minimum values of these parameters are: . The DS1075 . SIE 101697 7/16 ...
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... DS1075 t (min LOW I t (max LOW I Elow t (min SEI I t (max SEI I Ehigh NOTE: In each case there will be a small additional delay due to internal propagation delays. POWER–DOWN CONTROL If the PDN bit is set to “1”, the PDN/SELX pin can be used to power– ...
Page 9
... TTL–EQUIVALENT PORT PINS RX TX Programming mode is entered by simply powering up the DS1075 with a pull–up of approximately 5K . This will pull the IN/OUT pin above V on power–up and initi- IH ate the programming mode, causing the DS1075 to internally release the IN/OUT pin (after t ...
Page 10
... This command allows the bus master to read the DS1075’s MUX register. TRANSACTION/DATA Immediately following the Function Command, the nine data bits are written to or read from the DS1075. This data is written/read lsb first. The following diagrams illustrate the timing. Once data transfer is complete a ...
Page 11
... For a read data time slot “0” transmitted, the delay circuit determines how long the DS1075 will hold the data line low overriding the 1 gen- erated by the master. If the data bit is a “1”, the DS1075 will leave the read data time slot unchanged. t ...
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... RELEASE RESISTOR MASTER DS1075 DEFAULT REGISTER VALUES Unless ordered from the factory with specific register program values, the DS1075 is shipped with the follow- ing default register values: DIV = 0 0000 0000 (Programmable divider will divide by two) MUX = 0 0011 0100 OUT0 Disabled Power–Down Enabled, Select Disabled ...
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... – +125 C 260 C for 10 seconds ( MIN TYP MAX UNITS 4. –4 mA, 2 MIN = =5.25V =5.25V – =5.25V – 0.8 uA DS1075 = 5V + 5%) CC NOTES 101697 13/16 ...
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... DS1075 AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITION Output Frequency Tolerance Combined Freq. Variation f Over temp and O voltage Long Term Stability f O External clock Maximum Input Maximum Input f f OSCIN OSCIN Frequency Crystal reference Minimum Output f OUT Frequency Power–Up Time ...
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... LOW LOW pdn OUTH t 0 pdn pdn OUTH t 0 pdn t stab t stab DS1075 MAX OUTH M t OUTH Ehigh Elow + t OUTH M t OUTH + t OUTH M t OUTH ...
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... Please review this summary carefully. 1. Page 1, description, second paragraph. Word change 2. Page 14, AC electrical characteristic. Add Long Term Stability and new spec. The following represent the key differences between 05/01/97 and 10/15/97 version of the DS1075 data sheet. Please review this summary carefully. 1. Status Change (REMOVE PRELIMINARY). 101697 16/16 ...