upd75212a Renesas Electronics Corporation., upd75212a Datasheet
upd75212a
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upd75212a Summary of contents
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SINGLE-CHIP MICROCOMPUTER DESCRIPTION The PD75212A is a microcomputer with a CPU capable of 1-, 4-, and 8-bit data processing, ROM, RAM, I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, ...
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ORDERING INFORMATION Ordering Code PD75212ACW- PD75212AGF- -3BE Remarks is a ROM code number. Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and ...
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LIST OF FUNCTIONS Item Instruction execution time • 0.95, 1.91, 15.3 s (Main system clock : 4.19 MHz operation) • 122 s (Subsystem clock : 32.768 kHz operation) On-chip memory ROM 12160 RAM 512 4 bits General register • 4-bit ...
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PIN CONFIGURATION (TOP VIEW) ......................................................................................................... 6 2. BLOCK DIAGRAM ...................................................................................................................................... 8 3. PIN FUNCTIONS ........................................................................................................................................ 9 3.1 PORT PINS ............................................................................................................................................................. 9 3.2 NON-PORT PINS .................................................................................................................................................. 10 3.3 PIN INPUT/OUTPUT CIRCUIT LIST .................................................................................................................... 11 3.4 UNUSED PINS TREATMENT .............................................................................................................................. 12 ...
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RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 66 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 67 APPENDIX B. RELATED DOCUMENTS ......................................................................................................... 68 PD75212A 5 ...
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PIN CONFIGURATION (TOP VIEW) P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 P23/BUZ P41 52 P42 53 P43 54 PPO ...
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PIN NAME P00-P03 : Port 0 P10-P13 : Port 1 P20-P23 : Port 2 P30-P33 : Port 3 P40-P43 : Port 4 P50-P53 : Port 5 P60-P63 : Port 6 PH0-PH3 : Port H T0-T15 : Digit Output 0-15 S0-S15 ...
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BASIC INTERVAL TIMER PROGRAM INTBT COUNTER(14) TI0/P13 TIMER/EVENT COUNTER #0 INTT0 TIMER/PULSE GENERATOR PPO INTTPG PROGRAM MEMORY SI/P03 12160 SERIAL SO/P02 INTERFACE SCK/P01 INTSIO INT0/P10 INT1/P11 INTERRUPT INT2/P12 CONTROL INTW INT4/P00 WATCH TIMER BUZ/P23 CY ALU GENERAL REG. ROM DECODE ...
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PIN FUNCTIONS 3.1 PORT PINS Dual- Pin Name I/O Function Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO P03 Input SI P10 INT0 Input P11 INT1 P12 INT2 P13 TI0 P20 Input/ ––– output P21 ––– P22 ...
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NON-PORT PINS Dual- Pin Name I/O Function Pin Output ––– T10/S15 to PH3 to PH0 T13/S12 T14/S11, ––– T15/S10 PPO Output ––– TI0 Input P13 SCK Input/output P01 SO Input/output P02 SI ...
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PIN INPUT/OUTPUT CIRCUIT LIST TYPE P-ch IN N-ch CMOS-Specified Input Buffer TYPE B IN Schmitt-Triggered Input Having Hysteresis Characteristics TYPE D data output disable Push-Pull Output which can be Set to Output High Impedance (with Both ...
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UNUSED PINS TREATMENT Pin P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 to P12/INT2 P13/TI0 P20 to P22 P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 PPO T15/S10 to T14/S11 T10/S15/PH3 ...
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P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS P00/INT4 and RESET pins have the function (especially for IC test) to test addition to the functions described in sections 3.1 and 3.2. The test mode is set when a voltage larger ...
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MEMORY CONFIGURATION Program memory (ROM) ................................. 12160 words • 0000H to 0001H : Vector table for writing program start address by reset • 0002H to 000FH : Vector table for writing program start address by interrupt • 0020H to ...
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MBE RBE Internal Reset Start Address (Most Significant 6 Bits) Internal Reset Start Address (Least Significant 8 Bits MBE RBE INTBT/INT4 ...
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Stack Area General Static RAM (512 4) Display Data Memory, etc. 16 Fig. 4-2 Data Memory Map General Register (32 Area 256 ...
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PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports have the following three functions. CMOS input CMOS input/output P-ch open-drain, high-voltage, high-current output : 4 Total Port Name Function PORT0 4-bit input Always read or test possible irrespective of the dual-function ...
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CLOCK GENERATOR The clock generator operations are determined by the processor clock control register (PCC) and the system clock control register (SCC). The clock generator has two types: main system clock and subsystem clock. The instruction execution time can ...
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BASIC INTERVAL TIMER The basic interval timer has the following functions: Interval timer operation to generate reference time Watchdog timer application to detect inadvertent program loop Wait time select and count upon standby mode release Count contents read Fig. ...
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WATCH TIMER The PD75212A incorporates one channel of watch timer. The watch timer has the following functions. Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by IRQW. 0.5-second interval can be set with ...
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TIMER/EVENT COUNTER The PD75212A incorporates one channel of timer/event counter. The timer/event counter has the following functions. Program interval timer operation Event counter operation Count state read function Fig. 5-4 Timer/Event Counter Block Diagram TMn7 TMn6 TMn5 TMn4 TMn3 ...
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TIMER/PULSE GENERATOR The PD75212A incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions. (a) Functions available in the timer mode 8-bit interval timer operation ...
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Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode) Modulo Register H (8) TPGM3 MODH (8) TPGM1 f 1/2 x Frequency Divider 5.7 SERIAL INTERFACE The PD75212A serial interface has the following functions. Clocked 8-bit send/receive operation (simultaneous send/receive) ...
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P03/SI SIO0 Shift Register (8) *1 P02/SO P01/SCK * 1. CMOS output and N-ch open drain output switchable output buffer. 2. Instruction execution Fig 5-7 Serial Interface Block Diagram Internal Bus 8 SIO7 SIO SIOM7SIOM6SIOM5SIOM4SIOM3SIOM2SIOM1SIOM0 SO Output Latch Overflow ...
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FIP CONTROLLER/DRIVER The FIP controller/driver incorporated in the PD75212A has the following functions: Generates the segment and digit signals by automatically reading the display data memory executing DMA operation. Can select total of 26 display devices ...
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Fig. 5-8 FIP Controller/Driver Block Diagram Display Data Memory (64 4 Bits) Key Scan Registers (KS0, KS1) 12 Segment Data Latch (16) 10 High-Voltage Output Buffer 10 S0-S9 Note The FIP controller/driver can only operate in the high and intermediate-speeds ...
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POWER-ON FLAG (MASK OPTION) The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power- on reset signal is generated (See Fig. 8-1 Reset Signal Generator). The PONF is mapped at bit ...
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INTERRUPT FUNCTIONS The PD75212A has eight types of interrupt sources and can generate multiple interrupts with priority order also equipped with two types of test sources. INT2 is an edge detected testable input. The PD75212A interrupt control ...
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Fig. 6-1 Interrupt Control Circuit Block Diagram 2 2 IM1 IM0 Interrupt Enable Flag (IE INT IRQBT BT Both Edges INT4 IRQ4 Detection /P00 Circuit Edge INT0 Detection IRQ0 * /P10 Circuit Edge INT1 IRQ1 * Detection /P11 Circuit INTSIO ...
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STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the consumption in the program standby mode. Table 7-1 Operation Status in Standby Mode Set instruction STOP instruction System clock when set Setting enabled only with ...
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RESET FUNCTIONS The reset signal (RES) generator has a configuration shown in Fig. 8-1. RESET Power-On Reset Generator The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power voltage. ...
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Fig. 8-2 Reset Operation by Power-On Reset Supply Voltage 0 V Internal Reset Signal (RES) * Wait time does not include a time from RES signal generation to oscillation start. Fig. 8-3 Reset Operation by RESET Input RESET Input Operating ...
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Table 8-1 Hardware Statuses after Reset Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, IST1) Bank enable flags (MBE, RBE) Stack pointer (SP) Data memory (RAM) General registers ( ...
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INSTRUCTION SET (1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (For details, refer to RA75X Assembler Package User’s Manual Language ...
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Legend for operation description register; 4-bit accumulator register register register register register register register XA ...
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Description of symbols in the addressing area column * MBE • MBS (MBS = MBE = (00H to 7FH ...
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Mnemonic Operands Note 1 MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A mem reg XA, ...
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Note Mnemonic Operand MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, ...
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Note 1 Mnemonic Operands RORC A A NOT INCS reg rp1 @HL mem DECS reg rp' SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' SET1 CY CLR1 CY SKT CY NOT1 CY Note 1. Instruction ...
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Note Mnemonic Operands SET1 mem.bit fmem.bit pmem.@ mem.bit mem.bit CLR1 fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit CY, fmem.bit OR1 CY, ...
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Note Mnemonic Operands CALL !addr CALLF !faddr RET RETS RETI PUSH rp BS POP PORTn * XA, PORTn OUT PORTn PORTn, XA HALT STOP NOP SEL RBn MBn * MBE ...
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Note Mnemonic Operands GETI * taddr * TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Note Instruction Group 42 No. of Machine Operation Bytes Cycle 1 3 • TBR instruction PC (taddr) +(taddr+1) 13–0 4–0 ...
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MASK OPTION SELECTION The PD75212A has the following mask options enabling or disabling on-chip components. (1) Pin Pin P60 to P63 T0/T9 T10/S15/PH3 to T13/S12/PH0 T14/S11, T15/S10 XT1, XT2 Note system not using ...
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APPLICATION BLOCK DIAGRAM 11.1 VCR TIMER TUNER Main Power Supply Power Failure Detection LPF Electronic Tuner Tape Count Pulse Tape Up/Down SCK System Controller SO Microcomputer SI PD75104/75106 EEPROM™ PD6252 44 + Super Capacitor INT4 ...
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CD PLAYER SIO SCK Servo SI/SO Control IC Loading Circuit BUZ BZ X1 11.3 ECR Main Power Supply Power Failure Detection RAM Printer 14 T0–S13 Fluorescent Display Panel (FIP) S0–S11 12 12 Segments PD75212A Key Matrix PORT6 (12 INT0 ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ( PARAMETER SYMBOL Power supply voltage LOAD V PRE Input voltage Output voltage V OD Output current high I OH Output current low I ...
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Calculation of total loss Design so that the sum of the following three power consumption values for the PD75212ACW/GF will be less than the total loss P (It is recommended to use the system with ...
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MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = – RESONATOR RECOMMENDED CIRCUIT X1 X2 Ceramic resonator Crystal resonator External clock PD74HCU04 * 1. Refer to RECOMMENDED OSCILLATOR CONSTANTS. 2. ...
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SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = – RECOMMENDED CIRCUIT RESONATOR XT1 XT2 Crystal R resonator XT1 XT2 External Leave Open clock * 1. Recommended resonators are shown in following page. 2. Oscillator characteristics only. ...
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RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK : CERAMIC OSCILLATOR (Ta = –40 to +85 C) MANUFACTURER PRODUCT NAME CSA 2.00MG CSA 4.19MG CSA 4.91MG Murata Mfg. Co., Ltd. CAT 2.00MG CST 4.19MG CST 4.91MG KBR–2.0MS KBR–4.0MS Kyocera Corp. KBR–4.19MS KBR–4.19MS ...
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DC CHARACTERISTICS (Ta = – PARAMETER SYMBOL V IH1 V IH2 Input voltage high V IH3 V IH4 V IL1 V Input Voltage low IL2 V IL3 Output voltage high V OH Output voltage low V ...
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The following external circuit is recommended. PD75212A PRE V LOAD Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 3. When the processor clock control register ...
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AC CHARACTERISTICS (Ta = – PARAMETER SYMBOL CPU clock cycle time (minimum instruction t CY execution time = 1 machine cycle TI0 input frequency TIH TI0 input high and low- ...
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CPU clock ( ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time t characteristics for power supply voltage ...
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AC Timing Test Points (Except X1 and XT1 Inputs) 0.75 V 0.2 V Clock Timing X1 Input XT1 Input TI0 Timing TI0 0. Test Points ...
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Serial Transfer Timing SCK SI SO Interrupt Input Timing INT0,1,2,4 RESET Input Timing RESET 56 t KCY SIK KSI Input Data t KSO Output Data t t INTL INTH t RSL PD75212A ...
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DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 C) PARAMETER SYMBOL Data retention power V DDDR supply voltage Data retention power I DDDR supply current *1 Release signal set time t SREL ...
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Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal STOP Instruction Execution Standby Release Signal (Interrupt Request) 58 HALT Mode STOP Mode Data Retention Mode t V SREL DDDR PD75212A Operating Mode t WAIT ...
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CHARACTERISTIC CURVES 5000 1000 500 100 Remarks Values of the processor clock control register (PCC) are indicated in parenthesis 4.19 MHz ...
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–20 V – –10 – (Ports ...
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(Ports Output Voltage Low – ...
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(T0 to T15 – PRE V – PRE ...
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PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" ...
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PIN PLASTIC QFP (14 20 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. 64 detail of ...
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QFP for ES (reference) (unit : mm) 14.2 12 1.0 0.4 Bottom View Note 1. Care is needed since the metal cap is con- nected to pin 26 and set ...
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RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mount Manual” (IEI-1207). For soldering methods and conditions other than those ...
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APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for the development of systems using the PD75212A. IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75216ACW-R EP-75216AGF-R EV-9200G-64 PG-1500 PA-75P216ACW PA-75P218GF PA-75P218KB IE control program PG-1500 controller RA75X relocatable assembler * 1. Maintenance product ...
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APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name User’s Manual Instruction Application Table Application Note 75X Series Selection Guide Development Tools Related Documents Document Name IE-75000-R/IE-75001-R User’s Manual IE-75000-R-EM User’s Manual EP-75216ACW-R User’s Manual EP-75216AGF-R User’s Manual PG-1500 User’s ...
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PD75212A 69 ...
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No part of this document may be copied or reproduced in any form or by any means without the prior written No part of this document may be copied or reproduced in any form or by any means ...