lsm330dlc STMicroelectronics, lsm330dlc Datasheet

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lsm330dlc

Manufacturer Part Number
lsm330dlc
Description
Inemo Inertial Module 3d Accelerometer And 3d Gyroscope
Manufacturer
STMicroelectronics
Datasheet

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Features
Application
Description
The LSM330DLC is a system-in-package
featuring a 3D digital accelerometer and a 3D
digital gyroscope.
Table 1.
September 2011
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Analog supply voltage: 2.4 V to 3.6 V
Digital supply voltage IOs: 1.8 V
Low power mode
Power-down mode
3 independent acceleration channels and 3
angular rate channels
±2 g/±4 g/±8 g/±16 g dynamically selectable
full scale
±250/±500/±2000 dps dynamically selectable
full scale
SPI/I
Programmable interrupt generator for free-fall
and motion detection
ECOPACK
GPS navigation systems
Impact recognition and logging
Gaming and virtual reality input devices
Motion activated functions
Intelligent power saving for handheld devices
Vibration monitoring and compensation
Free-fall detection
6D orientation detection
LSM330DLCTR
Part number
LSM330DLC
2
C serial interface (16-bit data output)
Device summary
®
RoHS and “Green” compliant
Temperature range [°C]
-40 to +85
-40 to +85
Doc ID 022162 Rev 1
3D accelerometer and 3D gyroscope
ST’s family of MEMS sensor modules leverages
the robust and mature manufacturing processes
already used for the production of micromachined
accelerometers.
The various sensing elements are manufactured
using specialized micromachining processes,
while the IC interfaces are developed using a
CMOS technology that allows the design of a
dedicated circuit which is trimmed to better match
the sensing element characteristics.
The LSM330DLC has dynamically user-
selectable full scale acceleration range of
±2 g/±4 g/±8 g/±16 g and angular rate of
±250/±500/±2000 deg/sec.
The accelerometer and gyroscope sensors can
be either activated or separately put in Low
power/Power-down mode for applications
optimized for power saving.
The LSM330DLC is available in a plastic land grid
array (LGA) package.
LGA-28L (4x5x1.1 mm)
Package
iNEMO inertial module:
LGA-28L (4x5x1.1 mm)
LSM330DLC
Tape and reel
Packing
Preliminary data
Tray
www.st.com
1/67
67

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lsm330dlc Summary of contents

Page 1

... The accelerometer and gyroscope sensors can be either activated or separately put in Low power/Power-down mode for applications optimized for power saving. The LSM330DLC is available in a plastic land grid array (LGA) package. Temperature range [°C] -40 to +85 LGA-28L (4x5x1.1 mm) -40 to +85 ...

Page 2

... FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 4.4.2 2/67 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6D/4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 “Sleep-to-wake” and “Return to sleep” FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 022162 Rev 1 LSM330DLC ...

Page 3

... LSM330DLC 4.4.3 4.4.4 4.4.5 4.4.6 4.5 Level-sensitive / Edge-sensitive data enable . . . . . . . . . . . . . . . . . . . . . . 25 4.5.1 4.5.2 4.6 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.1 6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.1 6.2.2 6.2.3 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 CTRL_REG1_A (20h 8.2 CTRL_REG2_A (21h 8.3 CTRL_REG3_A (22h 8.4 CTRL_REG4_A (23h 8.5 CTRL_REG5_A (24h 8.6 CTRL_REG6_A (25h ...

Page 4

... CTRL_REG3_G (22h 8.30 CTRL_REG4_G (23h 8.31 CTRL_REG5_G (24h 8.32 REFERENCE_G (25h 8.33 OUT_TEMP_G (26h 8.34 STATUS_REG_G (27h 8.35 OUT_X_L_G (28h), OUT_X_H_G (29h 8.36 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh 8.37 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh 8.38 FIFO_CTRL_REG_G (2Eh 8.39 FIFO_SRC_REG_G (2Fh 8.40 INT1_CFG_G (30h 8.41 INT1_SRC_G (31h 8.42 INT1_THS_XH_G (32h 8.43 INT1_THS_XL_G (33h 8.44 INT1_THS_YH _G (34h 4/67 Doc ID 022162 Rev 1 LSM330DLC ...

Page 5

... LSM330DLC 8.45 INT1_THS_YL_G (35h 8.46 INT1_THS_ZH_G (36h 8.47 INT1_THS_ZL_G (37h 8.48 INT1_DURATION_G (38h Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Doc ID 022162 Rev 1 Contents 5/67 ...

Page 6

... FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 38. FIFO_CTRL_REG_A register description Table 39. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 40. FIFO_SRC_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 41. FIFO_SRC_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 42. INT1_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 43. INT1_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 44. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 45. INT1_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 46. INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 47. INT1_THS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 48. INT1_THS_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6/67 Doc ID 022162 Rev 1 LSM330DLC ...

Page 7

... LSM330DLC Table 49. INT1_DURATION_Aregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 50. INT1_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 51. CLICK_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 52. CLICK_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 53. CLICK_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 54. CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 55. CLICK_THS_A register Table 56. CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 57. TIME_LIMIT_A register Table 58. TIME_LIMIT_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 59. TIME_LATENCY_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 60. TIME_LATENCY_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 61. TIME_WINDOW_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 62. ...

Page 8

... Table 103. INT1_THS_YL_G register Table 104. INT1_THS_YL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 105. INT1_THS_ZH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 106. INT1_THS_ZH_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 107. INT1_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 108. INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 109. INT1_DURATION_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 110. INT1_DURATION_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 111. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8/67 Doc ID 022162 Rev 1 LSM330DLC ...

Page 9

... Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10. Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = Figure 12. Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 13. LSM330DLC electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 15. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 16. Multiple-byte SPI read protocol (2-byte example Figure 17. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 18 ...

Page 10

... Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. LSM330DLC block diagram Sensing Block ( Ω Feedback+ Feedback- Drive- Drive+ CONTROL LOGIC INTERRUPT GEN. 10/67 Sensing Interface CHARGE AMPLIFIER + A/D MUX converter - CHARGE ...

Page 11

... LSM330DLC 1.2 Pin description Figure 2. Pin connection DIRECTION OF DETECTABLE ACCELERATIONS Z + Ω + Ω + Ω DIRECTION OF DETECTABLE ANGULAR RATES Table 2. Pin description Pin INT1_A INT2_A INT1_G DRDY_G/INT2_G DEN_G CAP Name ...

Page 12

... SPI serial data output (SDO least significant bit of the device address (SA0 serial data (SDA) SDA_A/G SPI serial data input (SDI) 3-wire interface serial data output (SDO) Doc ID 022162 Rev 1 LSM330DLC Function 2 C communication 2 C disabled communication 2 C disabled) ...

Page 13

... LSM330DLC 2 Module specifications 2.1 Mechanical characteristics @ Vdd = 3V °C unless otherwise noted Table 3. Mechanical characteristics Symbol Parameter Linear acceleration measurement LA_FS (2) range Angular rate G_FS measurement range LA_So Linear acceleration sensitivity G_So Angular rate sensitivity Linear acceleration sensitivity LA_So change vs. temperature Angular rate sensitivity change vs. ...

Page 14

... Typical specifications are not guaranteed. 2. Verified by wafer level test and measurement of initial offset and sensitivity. 3. Typical zero-g level offset value after MSL3 preconditioning. 4. Offset can be eliminated by enabling the built-in high-pass filter. 14/67 Test conditions Min ±250 dps Doc ID 022162 Rev 1 LSM330DLC (1) Typ. Max. Unit Hz 0.03 dps/ -40 +85 ° ...

Page 15

... LSM330DLC 2.2 Electrical characteristics @ Vdd = °C unless otherwise noted Table 4. Electrical characteristics Symbol Parameter Vdd Supply voltage Vdd_IO Power supply for I/O Accelerometer current LA_Idd consumption in Normal mode Accelerometer current LA_IddLowP consumption in Low power mode Accelerometer current LA_IddPdn consumption in Power-down mode ...

Page 16

... Electrical characteristics Symbol Parameter Temperature sensor output TSDr change vs. temperature TODR Temperature refresh rate Top Operating temperature range 1. Typical specifications are not guaranteed. b. The product is factory calibrated at 3.0 V. 16/67 (b) Test condition Min. - -40 Doc ID 022162 Rev 1 LSM330DLC (1) Typ. Max. Unit -1 °C/digit 1 Hz +85 °C ...

Page 17

... LSM330DLC 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and T Table 6. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time th(SI) SDI input hold time ...

Page 18

... I C slave timing diagram e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports 18/ standard mode (1) Min Max 0 100 4.7 4.0 250 0.01 3.45 1000 300 4 4.7 4 4.7 (e) Doc ID 022162 Rev 1 LSM330DLC . OP ( fast mode Min Max 0 400 1.3 0.6 100 0 0.9 ( 0.1C 300 b ( 0.1C 300 b ...

Page 19

... LSM330DLC 2.5 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...

Page 20

... This value changes very little over temperature and over time. 20/67 Table 3. The zero-g level tolerance Doc ID 022162 Rev 1 LSM330DLC ...

Page 21

... LSM330DLC 4 Functionality The LSM330DLC is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope. The device includes specific sensing elements and two IC interfaces capable to measuring both the acceleration and angular rate applied to the module and to provide a signal to external applications through an SPI/I ...

Page 22

... FIFO The LSM330DLC embeds 32 slots of data FIFO for each of the three output channels and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO ...

Page 23

... LSM330DLC 4.2.5 Stream-to-FIFO mode In Stream-to-FIFO mode, data from X, Y and Z measurement is stored in the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit in the register) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of the until it is full (32 slots of 8 -bit data for X, Y and Z). When full, the FIFO discards the older data as the data new arrives ...

Page 24

... FIFO The LSM330DLC embeds 32 slots of 16-bit data FIFO for each of the three output channels: yaw, pitch and roll. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but can wake up only when needed and burst the significant data out from the FIFO ...

Page 25

... LSM330DLC Figure 7. FIFO mode 4.4.3 Stream mode In Stream mode, data from yaw, pitch and roll measurement is stored in the FIFO. A watermark interrupt can be enabled and set as in FIFO mode.The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). When full, the FIFO discards the older data as the new data arrives ...

Page 26

... Functionality Figure 8. Stream mode 26/ Doc ID 022162 Rev 1 LSM330DLC AM07234v1 ...

Page 27

... LSM330DLC 4.4.4 Bypass-to-stream mode In Bypass-to-stream mode, the FIFO starts operating in Bypass mode and once a trigger event occurs (related to mode. Refer to Figure 9 Figure 9. Bypass-to-stream mode Empty x 4.4.5 Stream-to-FIFO mode In Stream-to-FIFO mode, data from yaw, pitch and roll measurement is stored in the FIFO. A ...

Page 28

... Z with autoincremental address) operations can be used. When data included in starts to read information from addr 4.5 Level-sensitive / Edge-sensitive data enable The LSM330DLC allows external trigger level recognition through the enabling of the EXTRen and LVLen bits in the Level-sensitive or Edge-sensitive trigger. 28/67 x ...

Page 29

... LSM330DLC Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0) Level-sensitive Trigger enabled on X-Axis Xen=1,Yen=Zen=0 Level-sensitive Trigger enabled on Y-axis Yen=1, Xen=Zen=0 Level-sensitive Trigger enabled on Z-axis Zen=1, Xen=Yen=0 4.5.1 Level-sensitive trigger stamping Once enabled, DEN level replaces the LSb of the axes, configurable through the Xen, Yen, Zen bits in the internally-selected ODR ...

Page 30

... The IC interface is factory calibrated for sensitivity and zero level. The trimming values are stored in the device in non volatile memory. Any time the device is turned on, the trimming parameters are downloaded to the registers to be used during normal operation. This allows use of the device without further calibration. 30/67 Doc ID 022162 Rev 1 LSM330DLC ...

Page 31

... LSM330DLC 5 Application hints Figure 13. LSM330DLC electrical connection Vdd_IO C2 100 nF GND INT1_A INT2_A INT1_G DRDY_G DEN_G 10nF(25V) CAP *C1 GND Vdd C3 C4 100 nF 10 µF GND GND Digital signal from/to signal controller. Signals levels are defined by proper selection of Vdd 5.1 External capacitors The device core is supplied through the Vdd line. Power supply decoupling capacitors (C2, C3=100 nF ceramic, C4=10 µ ...

Page 32

... The LGA package is compliant with ECOPACK qualified for soldering heat resistance according to JEDEC J-STD-020D. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems. 32/67 ® , RoHS and “Green” standards Doc ID 022162 Rev 1 LSM330DLC ...

Page 33

... LSM330DLC 6 Digital interfaces The registers embedded in the LSM330DLC may be accessed through both the I serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. To select/exploit the I Table 10. Serial interface pin description Pin name CS_A CS_G SCL_A/G SDA_A/G SDO_A SDO_G 2 6 ...

Page 34

... The I C embedded in the LSM330DLC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST), a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSb enables address auto increment. ...

Page 35

... LSM330DLC Data transfer only continues when the receiver is ready for another byte and releases the data line slave receiver does not acknowledge the slave address (i. not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave ...

Page 36

... Digital interfaces 6.2 SPI bus interface The LSM330DLC SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface interacts with the outside world through 4 wires: CS, SPC, SDI and SDO (SPC, SDI, SD0 are common). Figure 14. Read and write protocol ...

Page 37

... LSM330DLC 6.2.1 SPI read Figure 15. SPI read protocol CS SPC SDI SDO The SPI read command is performed with 16 clock pulses. A multiple-byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading ...

Page 38

... AD5 AD2 AD 1 AD0 DI7 D I6 DI5 D I4 DI3 DI2 DI1 DI0 DI15 DI13 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD 0 register. Doc ID 022162 Rev 1 LSM330DLC DI3 DI2 DI1 DI0 AM10132V1 AM10133V1 ...

Page 39

... LSM330DLC Figure 19. SPI read protocol in 3-wire mode CS SPC SDI/O RW The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. ...

Page 40

... Doc ID 022162 Rev 1 LSM330DLC Default Comment Binary Reserved 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 00000000 010 0100 00000000 010 0101 00000000 010 0110 00000000 010 0111 00000000 ...

Page 41

... LSM330DLC Table 18. Register address map (continued) Name address TIME_LATENCY_A Table 16 TIME_WINDOW_A Table 16 Act_THS Table 16 Act_DUR Table 16 Reserved Table 17 WHO_AM_I_G Table 17 Reserved Table 17 CTRL_REG1_G Table 17 CTRL_REG2_G Table 17 CTRL_REG3_G Table 17 CTRL_REG4_G Table 17 CTRL_REG5_G Table 17 REFERENCE_G Table 17 OUT_TEMP_G Table 17 STATUS_REG_G Table 17 OUT_X_L_G Table 17 OUT_X_H_G ...

Page 42

... Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 42/67 Doc ID 022162 Rev 1 LSM330DLC ...

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... LSM330DLC 8 Register descriptions The device contains a set of registers which are used to control its behavior and to retrieve acceleration, angular rate and temperature data. The register addresses, made bits, are used to identify them and to write the data through the serial interface. 8.1 CTRL_REG1_A (20h) Table 19 ...

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... Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode Autoreset on interrupt event (1) 0 I1_DRDY1 I1_DRDY2 CLICK interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) AOI1 interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) Doc ID 022162 Rev 1 LSM330DLC HPCLICK HPIS2 HPIS1 I1_WTM I1_OVERRUN -- ...

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... LSM330DLC Table 26. CTRL_REG3_A description (continued) I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN 8.4 CTRL_REG4_A (23h) Table 27. CTRL_REG4_A register (1) 0 BLE 1. This bit must be set to ‘0’ for correct operation. Table 28. CTRL_REG4_A description BLE FS1-FS0 HR SIM 8.5 CTRL_REG5_A (24h) Table 29. CTRL_REG5_A register BOOT FIFO_EN 1. This bit must be set to ‘0’ for correct operation. ...

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... Click interrupt on INT2_A. Default value 0. Interrupt 1 function enabled on INT2_A. Default 0. Boot on INT2_A. 0: interrupt active high; 1: interrupt active low. Ref5 Ref4 Ref3 Reference value for interrupt generation. Default value: 0 YOR XOR ZYXDA Doc ID 022162 Rev 1 LSM330DLC -- H_LACTIVE -- Ref2 Ref1 Ref0 ZDA YDA XDA ...

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... LSM330DLC Table 36. STATUS_REG_A register description (continued) YOR Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data) XOR X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data) ZYXDA X, Y and Z axis new data available ...

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... FM0 0 Bypass mode 1 FIFO mode 0 Stream mode 1 Trigger mode EMPTY FSS4 FSS3 ZLIE/ YHIE/ ZDOWNE YUPE mode, “Interrupt mode” Doc ID 022162 Rev 1 LSM330DLC FIFO mode FSS2 FSS1 FSS0 YLIE/ XHIE/ XLIE/ YDOWNE XUPE XDOWNE Table 44: Inter- Table 44: Interrupt ...

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... LSM330DLC Table 43. INT1_CFG_A description (continued) YHIE/ Enable interrupt generation on Y high event or on direction recognition. Default YUPE value: 0 (0: disable interrupt request; 1: enable interrupt request.) YLIE/ Enable interrupt generation on Y low event or on direction recognition. Default YDOWNE value: 0 (0: disable interrupt request; 1: enable interrupt request.) XHIE/ Enable interrupt generation on X high event or on direction recognition ...

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... bits set the minimum duration of the Interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 50/67 INT1_SRC_A register THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Duration value. Default value: 000 0000 Doc ID 022162 Rev 1 LSM330DLC if the latched option was THS3 THS2 THS1 THS0 D0 ...

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... LSM330DLC 8.18 CLICK_CFG _A (38h) Table 51. CLICK_CFG_A register -- -- Table 52. CLICK_CFG_A description 8.19 CLICK_SRC_A (39h) Table 53. CLICK_SRC_A register -- IA Table 54. CLICK_SRC_A description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) DCLICK Double CLICK-CLICK enable. Default value: 0 (0:double CLICK-CLICK detection dis- ...

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... CLICK-CLICK threshold. Default value: 000 0000 TLI5 TLI4 TLI3 CLICK-CLICK Time limit. Default value: 000 0000 TLA5 TLA4 TLA3 CLICK-CLICK time latency. Default value: 000 0000 TW5 TW4 TW3 Doc ID 022162 Rev 1 LSM330DLC Ths2 Ths1 Ths0 TLI2 TLI1 TLI0 TLA2 TLA1 TLA0 TW2 TW1 TW0 ...

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... LSM330DLC Table 62. TIME_WINDOW_A description TW7-TW0 8.24 Act_THS (3Eh) Table 63. Act_THS register -- Acth6 Table 64. Act_THS description Acth[6-0] 8.25 Act_DUR (3Fh) Table 65. Act_DUR register ActD7 ActD6 Table 66. Act_DUR description ActD[7-0] 8.26 WHO_AM_I_G (0Fh) Table 67. WHO_AM_I_G register 1 1 Device identification register. 8.27 CTRL_REG1_G (20h) Table 68. CTRL_REG1_G register DR1 DR0 Table 69 ...

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... Normal / Sleep mode) according to the following table: Table 71. Power mode selection configuration Mode Power-down 0 54/67 BW <1:0> 190 01 190 10 190 11 190 00 380 01 380 10 380 11 380 00 760 01 760 10 760 11 760 PD Zen - Doc ID 022162 Rev 1 LSM330DLC ODR [Hz] Cut-off 12 12 100 100 Yen Xen - - ...

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... LSM330DLC Table 71. Power mode selection configuration Sleep 1 Normal 1 8.28 CTRL_REG2_G (21h) Table 72. CTRL_REG2_G register EXTRen LVLen Table 73. CTRL_REG2_G description Edge-sensitive trigger Enable: Default value: 0 EXTRen (0: external trigger disabled; 1: External trigger enabled) Level-sensitive trigger Enable: Default value: 0 LVLen (0: level sensitive trigger disabled; 1: level sensitive trigger enabled) HPM1- High-pass filter mode selection ...

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... Data LSb @ lower address; 1: Data MSb @ lower address) Full scale selection. Default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) 3-wire SPI Serial interface read mode enable. Default value: 0 (0: 3-wire Read mode disabled; 1: 3-wire read enabled). Doc ID 022162 Rev 1 LSM330DLC 0.09 0.18 0.045 0.09 I2_WTM ...

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... LSM330DLC 8.31 CTRL_REG5_G (24h) Table 80. CTRL_REG5_G register BOOT FIFO_EN Table 81. CTRL_REG5_G description BOOT FIFO_EN HPen INT1_Sel1- INT1_Sel0 Out_Sel1- Out_Sel1 Figure 20. INT1_Sel and Out_Sel configuration block diagram ADC LPF1 8.32 REFERENCE_G (25h) Table 82. REFERENCE_G register Ref7 Ref6 Table 83. REFERENCE_G register description Ref 7-Ref0 -- HPen INT1_Sel1 INT1_Sel0 Reboot memory content ...

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... OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) Y-axis angular rate data. The value is expressed as two’s complement. 58/67 Temp5 Temp4 Temp3 Temperature data (1LSb/deg - 8-bit resolution). The value is expressed as two’s complement. YOR XOR ZYXDA Doc ID 022162 Rev 1 LSM330DLC Temp2 Temp1 Temp0 ZDA YDA XDA ...

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... LSM330DLC 8.37 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) Z-axis angular rate data. The value is expressed as two’s complement. 8.38 FIFO_CTRL_REG_G (2Eh) Table 88. FIFO_CTRL_REG_G register FM2 FM1 Table 89. FIFO_CTRL_REG_G description FM2-FM0 FIFO mode selection. Default value: 00 (see WTM4-WTM0 FIFO threshold. Watermark level setting Table 90. FIFO mode configuration ...

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... INT1_SRC_G description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated high. Default value: 0 (0: no interrupt High event has occurred) 60/67 ZHIE ZLIE YHIE Doc ID 022162 Rev 1 LSM330DLC YLIE XHIE XLIE ...

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... LSM330DLC Table 96. INT1_SRC_G description ZL Z low. Default value: 0 (0: no interrupt Low event has occurred high. Default value: 0 (0: no interrupt High event has occurred low. Default value: 0 (0: no interrupt Low event has occurred high. Default value: 0 (0: no interrupt High event has occurred low ...

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... Interrupt threshold. Default value: 0000 0000 THSZ5 THSZ4 Interrupt threshold. Default value: 0000 0000 D5 D4 WAIT enable. Default value: 0 (0: disable; 1: enable) Duration value. Default value: 000 0000 Doc ID 022162 Rev 1 THSY3 THSY2 THSY1 THSZ11 THSZ10 THSZ9 THSZ3 THSZ2 THSZ1 LSM330DLC THSY0 THSZ8 THSZ0 D0 ...

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... LSM330DLC WAIT bit has the following meaning: Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold Wait =’1’: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register ...

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... Register descriptions Figure 22. Wait enabled 64/67 Doc ID 022162 Rev 1 LSM330DLC ...

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... LSM330DLC 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. Figure 23. LGA-28 (4x5x1.1 mm): mechanical data and package dimensions Ref ...

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... Revision history 10 Revision history Table 111. Document revision history Date 2-Sep-2011 66/67 Revision 1 Initial release. Doc ID 022162 Rev 1 LSM330DLC Changes ...

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... LSM330DLC Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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