si5310 Silicon Laboratories, si5310 Datasheet

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si5310

Manufacturer Part Number
si5310
Description
Precision Clock Multiplier/regenerator Ic
Manufacturer
Silicon Laboratories
Datasheet

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Features
Complete precision clock multiplier and clock regenerator device:
Applications
Description
The Si5310 is a fully integrated low-power clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. The clock regenerator operates
simultaneously, creating a “clean” version of the input clock by using the
clock synthesis phase-locked loop (PLL) to remove unwanted jitter and
square up the input clock’s rising and falling edges. The Si5310 uses
Silicon Laboratories patented DSPLL
jitter performance while eliminating the analog loop filter found in
traditional PLL designs with a digital signal-processing algorithm.
The Si5310 represents a new standard in low jitter, small size, low power,
and ease-of-use for clock devices. It operates from a single 2.5 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Rev. 1.3 6/08
RECISION
Performs clock multiplication to one
of two frequency ranges:
150–167 MHz or 600–668 MHz
Jitter generation as low as
0.5 ps
Accepts input clock from
9.4–668 MHz
SONET/SDH systems
Terabit routers
Digital cross connects
CLKIN+
CLKIN–
rms
for 622 MHz output
2
BUF
C
REFCLK+
REFCLK–
Phase-Locked
L O C K
2
DSPLL
Loop
MULTSEL
®
Copyright © 2008 by Silicon Laboratories
M
®
Optical transceiver modules
Gigabit Ethernet systems
Fibre channel
Regeneration
architecture to achieve superior
Regenerates a “clean”, jitter-
attenuated version of input clock
DSPLL™ technology provides
superior jitter performance
Small footprint: 4 x 4 mm
Low power: 310 mW typical
ROHS-compliant Pb-free
packaging option available
ULTIPLIER
Calibration
Bias Gen
REXT
BUF
BUF
2
2
CLKOUT+
CLKOUT–
/ R
PWRDN/CAL
MULTOUT+
MULTOUT–
LOL
EGENERATOR
REFCLK+
REFCLK–
REXT
GND
VDD
Ordering Information:
Pin Assignments
1
2
3
4
5
20 19 18 17 16
See page 21.
6
Si5310
Si5310
7
GND
Pad
IC
8
9
10
15
14
13
12
11
PWRDN
VDD
CLKOUT+
CLKOUT–
VDD
Si5310

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si5310 Summary of contents

Page 1

... PLL designs with a digital signal-processing algorithm. The Si5310 represents a new standard in low jitter, small size, low power, and ease-of-use for clock devices. It operates from a single 2.5 V supply over the industrial temperature range (– °C). ...

Page 2

... Si5310 2 Rev. 1.3 ...

Page 3

... PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8. Device Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.10. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.11. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.12. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.13. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions: Si5310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Rev ...

Page 4

... Si5310 1. Detailed Block Diagram CLKIN+ Phase Phase Phase Detector Detector Detector CLKIN– REFCLK+ REFCLK+ REFCLK– MULTSEL REXT Bias Bias Bias Generation Generation Generation 4 CLK VCO A/D DSP Divider n Lock Detector Calibration Rev. 1.3 CLKOUT+ Regen Retime Retime CLKOUT– c MULTOUT+ c MULTOUT– ...

Page 5

... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5310 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3. Typical Application Circuit" on page 11. ...

Page 6

... Si5310 Table 2. DC Characteristics 2.5 V ±5 – ° Parameter Supply Current MULTSEL = 0 MULTSEL = 1 Power Dissipation MULTSEL = 0 MULTSEL = 1 Common Mode Input Voltage (CLKIN, REFCLK) Input Voltage Range* (CLKIN+, CLKIN–, REFCLK+, REFCLK–) Differential Input Voltage Swing* (CLKIN, REFCLK) ...

Page 7

... Figure 3 — F Figure 3 — F Figure 2 –670 2.4 Figure 100 MULT 780 100 kHz–1 GHz — Rev. 1.3 Si5310 Typ Max Unit — 668 MHz — — 167 MHz — 100 ppm — 668 MHz — 167 ...

Page 8

... Si5310 Table 4. AC Characteristics (PLL Performance Characteristics 2.5 V ±5 – ° Parameter Jitter Tolerance (MULTSEL = 0, MULTOUT = 600 to 668 MHz) Jitter Tolerance (MULTSEL = 1, MULTOUT = 150 to 167 MHz) Jitter Generation (MULTOUT, CLKOUT) (MULTSEL = 0, MULTOUT = 600 to 668 MHz)* (measurement BW = 12kHz to 1MHz) Jitter Generation (MULTOUT, CLKOUT) ...

Page 9

... Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 T After falling edge of AQ PWRDN/CAL From the return of valid CLKIN LOL LOCK Rev. 1.3 Si5310 Min Typ Max Unit — kHz — kHz — 75 105 kHz — ...

Page 10

... Si5310 Table 5. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL = 0, MULTOUT = 600 to 668 MHz) Frequency (Hz) 37.5–41.75 MHz Clock Input < 300 25.0 25K 1.6 250K 1.6 > 1M 0.3 *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 6. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL = 1, MULTOUT = 150 to 167 MHz) Frequency (Hz) 9.375– ...

Page 11

... Typical Application Circuit Cloc k Input Sy s tem Ref erenc e Cloc k LV TTL Loss -of-Loc k Control Inputs Indicator CLKIN+ CLKOUT+ CLKIN– CLKOUT– Si5310 REFCLK+ MULTOUT+ REFCLK– MULTOUT– 0.1 μ Ω (1% ) 2200 Rev. 1.3 Si5310 Regenerated Cloc k Multiplied Cloc k 11 ...

Page 12

... Si5310 4. Functional Description The Si5310 is an integrated clock multiplier and clock regenerator device based on SIlicon Laboratories DSPLL™ technology. The DSPLL phase locks to the clock input signal (CLKIN) and generates a phase- locked output clock (MULTOUT multiple of the input clock frequency. The DSPLL is also employed to ...

Page 13

... Rev. 1.3 Si5310 CLKOUT MULTOUT output (MHz) (MHz) 9.72 155.52 19.44 155.52 38.88 155.52 38.88 622.08 77.76 155.52 77.76 622.08 — 155.52 155.52 622.08 311.04 622.08 — 622.08 9.77 156.25 19.53 156.25 39.06 156.25 39.06 625 78 ...

Page 14

... Note: When the Si5310 is configured as a 1:1 multiplier, the CLKOUT output is not valid. 4.4. Clock Regeneration The DSPLL is used to regenerate a jitter-attenuated version of the CLKIN input, resulting in a “clean” CLKOUT output with sharp rising and falling edges. The ...

Page 15

... Laboratories application note AN42 for suggested methods of generating the PWRDN/CAL signal for initiation of self-calibration. 4.10. Device Grounding The Si5310 uses the GND pad on the bottom of the 20- pin micro leaded package (MLP) for device ground. This level jitter pad should be connected directly to the analog supply ground ...

Page 16

... Si5310 4.11. Bias Generation Circuitry The Si5310 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption compared with traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND ...

Page 17

... RFCLK – Ω GND Si5310 VDD 2.5 kΩ REFCLK + 10 kΩ 2.5 kΩ 102 Ω 100 Ω REFCLK – 10 kΩ 0.1 μF GND Si5310 VDD 2.5 kΩ CLKIN + 10 kΩ 2.5 kΩ 102 Ω 100 Ω CLKIN – 10 kΩ 0.1 μF GND Rev. 1.3 Si5310 17 ...

Page 18

... CLKIN + 0.1 μF Si5310 VDD 100 Ω CLKOUT+, 0.1 μ Ω MULTOUT+ CLKOUT–, 0.1 μ Ω MULTOUT– 100 Ω VDD Rev. 1.3 Si5310 VDD 2.5 kΩ 102 Ω 10 kΩ GND VDD 2.5 kΩ 102 Ω 10 kΩ GND VDD 50 Ω 50 Ω VDD ...

Page 19

... REFCLK– Top View Figure 11. Si5310 Pin Configuration Table 11. Si5310 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. Supply Voltage. ...

Page 20

... Si5310 Table 11. Si5310 Pin Descriptions (Continued) Pin # Pin Name 12, 13 CLKOUT–, CLKOUT+ 15 PWRDN/CAL 16, 17 MULTOUT–, MULTOUT+ 19 MULTSEL I/O Signal Level Differential Clock Output. O CML The clock output signal is a regenerated version of the input clock signal present on CLKIN phase aligned with MULTOUT and is updated on the rising edge of MULTOUT ...

Page 21

... These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5310-C-GM Voltage Pb-Free 2.5 Yes Die Revision (R) Assembly Date (YWW Last digit of current year WW = Work week Rev. 1.3 Si5310 Temperature – °C 21 ...

Page 22

... Si5310 8. Package Outline Figure 12 illustrates the package details for the Si5310. Table 12 lists the values for the dimensions shown in the illustration. Figure 12. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 c — — D 4.00 BSC D2 1.95 2.10 e 0.50 BSC E 4.00 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...

Page 23

... A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended not place any signal or power plane vias in these “keep out” regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane. See Note 9 Gnd Pin Parameter Min 2.23 2.03 2.43 0.23 4.26 Rev. 1.3 Si5310 Dimensions Nom Max 2.25 2.28 2.08 2.13 — 0.50 BSC — 2.46 2.48 — ...

Page 24

... Si5310 OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Added "7. Top Mark" on page 21. Updated "8. Package Outline" on page 22. Added "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 23. Revision 1.1 to Revision 1.2 Added Pb-free packaging option in "6. Ordering Guide" on page 21. Revision 1.2 to Revision 1.3 Added "7. Top Mark" on page 21. ...

Page 25

... N : OTES Rev. 1.3 Si5310 25 ...

Page 26

... Si5310 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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