74LVC823ADB,112 NXP Semiconductors, 74LVC823ADB,112 Datasheet

IC 9BIT D FF POS-EDGE 24SSOP

74LVC823ADB,112

Manufacturer Part Number
74LVC823ADB,112
Description
IC 9BIT D FF POS-EDGE 24SSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
D-Type Busr
Datasheet

Specifications of 74LVC823ADB,112

Function
Master Reset
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
9
Frequency - Clock
200MHz
Delay Time - Propagation
3.7ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC823ADB
74LVC823ADB
935262540112
1. General description
2. Features
The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable
(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented
applications. The 9 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition, provided pin CE
is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all
flip-flops. When pin OE is LOW, the contents of the 9 flip-flops is available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 02 — 10 May 2004
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
9-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C.
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Product data sheet

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74LVC823ADB,112 Summary of contents

Page 1

D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 02 — 10 May 2004 1. General description The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL ...

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Philips Semiconductors 3. Quick reference data Table 1: GND = Symbol Parameter t , PHL t PLH t PHL f max [ input frequency in ...

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Philips Semiconductors 5. Functional diagram Fig 1. Functional diagram. Fig 2. Logic symbol. 9397 750 13128 Product data sheet 9-bit D-type flip-flop with 5 V tolerant inputs/outputs FF0 FF8 ...

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Philips Semiconductors Fig 4. Logic diagram. 9397 750 13128 Product data sheet 9-bit D-type flip-flop with 5 V tolerant inputs/outputs FF0 FF1 ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning 823 GND 12 Fig 5. Pin configuration SO24 and (T)SSOP24. 6.2 ...

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Philips Semiconductors Table 3: Symbol Functional description 7.1 Function table Table 4: Operating mode Clear Load and read register Load register and disable outputs Hold [ HIGH voltage level; h ...

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Philips Semiconductors 8. Limiting values Table 5: In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter ...

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Philips Semiconductors 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter [ +85 C amb V HIGH-level input voltage IH V LOW-level ...

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Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I 3-state output OFF-state OZ current I power-off leakage supply off I quiescent supply current CC I additional quiescent ...

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Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; see Figure 11 for test circuit. Symbol Parameter t set-up time set-up time removal time MR rem t hold time Dn to ...

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Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; see Figure 11 for test circuit. Symbol Parameter t clock pulse width HIGH or LOW W master reset pulse width HIGH or LOW see t set-up time ...

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Philips Semiconductors 12. Waveforms Fig 7. Clock to output propagation delays, clock pulse width and maximum clock pulse Fig 8. Data set-up and hold times for data and clock enable inputs to clock input. 9397 750 13128 Product data sheet ...

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Philips Semiconductors Fig 9. Master reset pulse width, master reset to clock removal time and master reset to Table 9: Supply voltage V CC 1.2 V 2 3.6 V 9397 750 13128 Product data sheet 9-bit ...

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Philips Semiconductors Fig 10. 3-state outputs enable and disable times. Table 10: Supply voltage V CC 1.2 V 2 3.6 V 9397 750 13128 Product data sheet 9-bit D-type flip-flop with 5 V tolerant inputs/outputs V ...

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Philips Semiconductors Fig 11. Load circuitry for switching times. Table 11: Supply voltage V CC 1.2 V 2 3.6 V [1] The circuit performs better when R 9397 750 13128 Product data sheet 9-bit D-type flip-flop ...

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Philips Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

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Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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Philips Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area ...

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Philips Semiconductors 14. Revision history Table 12: Revision history Document ID Release date 74LVC823A_2 20040510 • Modifications: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. • Table ...

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Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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