74HC574D,652 NXP Semiconductors, 74HC574D,652 Datasheet

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74HC574D,652

Manufacturer Part Number
74HC574D,652
Description
IC FLIP FLOP OCTAL D 3ST 20SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Type
D-Type Busr
Datasheet

Specifications of 74HC574D,652

Package / Case
20-SOIC (7.5mm Width)
Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
133MHz
Delay Time - Propagation
14ns
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
8
Logic Family
74HC
Logic Type
CMOS
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
150 ns
High Level Output Current
- 7.8 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3967-5
74HC574D
74HC574D
933715520652
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number Package
74HC574N
74HCT574N
74HC574D
74HCT574D
Ordering information
Temperature range
40 C to +125 C
40 C to +125 C
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition. When OE is LOW the contents of the 8 flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of
the OE input does not affect the state of the flip-flops.
The 74HC574; 74HCT574 is functionally identical to:
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 3 — 15 December 2010
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
74HC564: but has non-inverting outputs
74HC374; 74HCT374: but has a different pin arrangement
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Name
DIP20
SO20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
Product data sheet
Version
SOT146-1
SOT163-1

Related parts for 74HC574D,652

74HC574D,652 Summary of contents

Page 1

Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 3 — 15 December 2010 1. General description The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL specified in compliance with ...

Page 2

... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74HC574DB 74HCT574DB 40 C to +125 C 74HC574PW 74HCT574PW 4. Functional diagram Fig 1. Functional diagram FF1 Fig 2. Logic diagram 74HC_HCT574 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state … ...

Page 3

... NXP Semiconductors Fig 3. Logic symbol 5. Pinning information 5.1 Pinning 74HC574 74HCT574 GND 10 001aan290 Fig 5. Pin configuration DIP20 and SO20 74HC_HCT574 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state mna798 Fig Fig 6. All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2010 74HC574 ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin OE 1 D[0: GND Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output Functional description [1] Table 3. Function table Operating mode Load and read register Load register and disable output [ HIGH voltage level HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current 6 input I capacitance 74HCT574 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = 20   LOW-level output voltage = 20  6.0 mA ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions For type 74HC574 t propagation CP to Qn; see pd delay enable time OE to Qn; see disable time OE to Qn; see dis transition Qn; see t time V = 2.0 V ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions C power pF MHz dissipation V = GND capacitance For type 74HCT574 t propagation CP to Qn; see pd delay enable time OE to Qn; see 4 disable time OE to Qn; see dis transition Qn; see t time V = 4.5 V ...

Page 9

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) CP input Dn input Qn output ...

Page 10

... NXP Semiconductors OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 9. Enable and disable times Table 8. Measurement points Type 74HC574 74HCT574 74HC_HCT574 Product data sheet Octal D-type flip-flop ...

Page 11

... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC574 ...

Page 12

... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 13. Package outline SOT339-1 (SSOP20) ...

Page 15

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 16

... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification All information provided in this document is subject to legal disclaimers. ...

Page 17

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 18

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT574 Product data sheet Octal D-type flip-flop ...

Page 19

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations ...

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