si4420 Silicon Laboratories, si4420 Datasheet
si4420
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si4420 Summary of contents
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... FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the Si4420 can provide a clock signal for the microcontroller, avoiding the need for two crystals. ...
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... DETAILED FEATURE-LEVEL DESCRIPTION The Si4420 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application ...
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... Narrower receiver bandwidth (i.e. increased sensitivity) Higher data rate Crystal Oscillator The Si4420 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet ...
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... RF differential signal input/output 13 RF1 AIO RF differential signal input/output 14 VDD S Positive supply voltage 15 ARSSI AO Analog RSSI output nINT DI Interrupt input (active low) 16 VDI DO Valid data indicator output Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. Si4420 4 ...
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... C3 1u 100p 10p (optional) (optional 2. Si4420 12 5 (optional (optional (optional (optional) X1 10MHz Pin 6 TX Data input Connect to logic high RX Data output nFFS input Si4420 PCB Antenna Pin Data clock output FFIT output 5 ...
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... V cannot be higher than minimum Note 2: At maximum, V +1.5 V cannot be higher than 5 Min Max -0.5 6 -0.5 V +0.5 dd -0.5 V +1.5 (Note 1) dd -25 25 1000 -55 125 260 Min Max 2.2 5.4 V +1.5 (Note -1.5 (Note 1) dd Vdd+1.5 - 1.5 V cannot be lower than 1 Si4420 Units Units ...
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... MHz band All blocks disabled Crystal oscillator and baseband parts are on Programmable in 0.1 V steps 2.25 0 Si4420 = 2 Typ Max Units 0.3 µ ...
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... In band interferers in low bands (315, 433 MHz) Out of band interferers l f-f l > 4 MHz o LNA: high gain Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit ARRSI Si4420 Min Typ Max Units MHz 310.24 319.75 430 ...
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... Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step Conditions/Notes Programmable in 0.5 pF steps, tolerance +/- 10% After V has reached 90% of final value dd (Note 7) Crystal oscillator must be enabled to ensure proper calibration at startup (Note pure capacitive load Si4420 Min Typ Max Units 0 dBm 4 P -21 ...
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... The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray capacitance. Zantenna [Ohm] Lantenna [nH j179 98. j136 52.00 8.7 + j66 12. j63 11.20 www.silabs.com/integration Si4420 ). 10 ...
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... Select hold time (SCK falling edge to nSEL rising edge Select high time SHI t Data setup time (SDI transition to SCK rising edge Data hold time (SCK rising edge to SDI transition Data delay time OD Timing Diagram Si4420 Minimum value [ns ...
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... POR 8008h x1 x0 Crystal Load Capacitance [ 10.0 … 15 16.0 Si4420 12 ...
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... Related blocks RF front end, baseband, synthesizer, oscillator Baseband Power amplifier, synthesizer, oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer Si4420 POR 8208h 13 ...
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... Function of pin 16 0 Interrupt input 1 VDI output POR A680h C1 C2 315 1 31 433 1 43 868 2 43 915 POR C623h < (29*N is the maximal number of bit POR 9080h Si4420 ) bit 14 ...
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... Always on CR_LOCK DQD d0 SEL0 d1 SEL1 FAST IN0 MEDIUM IN1 SLOW IN2 LOGIC HIGH IN3 SET Q R/S FF CLR [kHz] reserved 400 340 270 200 134 reserved Si4420 VDI Y MUX 15 ...
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... RSSI [dBm] setth 0 -103 - - - - - Reserved Reserved Filter Type 0 Digital filter 1 Analog RC filter Si4420 POR C22Ch 16 ...
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... To restart the synchron pattern recognition, bit 1 should be cleared and set Synchron pattern 1 Always fill al FFOV ff ef* FFIT er** Note: * For details see the Configuration Setting Command ** For deatils see the Power Management Command Si4420 POR CA80h FIFO_LOGIC FIFO_WRITE _EN nFIFO_RESET 17 ...
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... MHz bands: 2.5 kHz to -16 f +15 f 868 MHz band: 5 kHz res res + res res 915 MHz band: 7.5 kHz + res res POR B000h received bits out LSB POR C4F7h Si4420 18 ...
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... Corrected frequency parameter to synthesizer CLK CLR NOTE: * VDI (valid data indicator internal signal of the controller. See the Receiver Setting Command for details. ** ATGL: toggling in each measurement cycle *** ASAME: logic high when the result is stable POR 9800h Si4420 19 ...
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... FSK=0 0 mp=1 and FSK fsk fsk f out f 0 mp=0 and FSK mp=1 and FSK POR B8AAh POR E196h Si4420 20 ...
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... The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command Ton Twake-up Twake- Si4420 POR C80Eh 2.25ms Ton Twake- POR C000h of the detector ...
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... The strength of the incoming signal is above the pre-programmed limit DQD Data quality detector output CRL Clock recovery locked ATGL Toggling in each AFC cycle OFFS(6) MSB of the measured frequency offset (sign of the offset value) OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits) Si4420 22 ...
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... Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. TX Register Simplified Block Diagram (Before Transmit) TX Register Simplified Block Diagram (During Transmit) Typical TX Register Usage Note: The content of the data registers are initialized by clearing bit et. Si4420 23 ...
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... The user can define the FIFO level (the number of received bits), which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. FIFO Read Example with FFIT Polling nSEL SCK nFFS FIFO read out SDO FIFO OUT FO+1 FO+2 FO+3 FFIT During FIFO access f cannot be higher than f SCK 4 FO+4 /4, where f is the crystal oscillator frequency. ref ref Si4420 24 ...
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... CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4420 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can variety of crystal types can be used. ...
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... Si4420 26 ...
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... Issuing FE00h command will trigger software reset. See the Wake-up Timer Command. Reset ramp line (100mV/ms) time Reset ramp line (100mV/ms) time ramp start.. Typical example when a switch-mode regulator is used to supply the radio, dd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC Si4420 27 ...
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... GND DEBUG GND 3, 2,2uF 1uF 100pF 10pF GND IC2 1 16 INT/VDI SDI NINT/VDI 15 ARSSI SCK ARSSI 14 VCC NSEL VDD 13 SDO RF1 12 NIRQ RF2 11 FSK/DATA/NFFS VSS 10 DCLK/CFIL NRES 9 CLK XTL/REF Q1 C2 10MHz IA4420-REVC 4,7nF GND GND Si4420 X1 GND 28 ...
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... PCB Layout Top View Bottom View Si4420 29 ...
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... Detail “A” Dimensions in Inches Nom. Max 0,035 0,041 0,009 0,010 0,197 0,201 0.252 BSC. 0,173 0,177 0,024 0,030 0.39 REF REF. 12 REF. Si4420 30 ...
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... RELATED PRODUCTS AND DOCUMENTS Si4420 Universal ISM Band FSK Transceiver DESCRIPTION Si4420 16-pin TSSOP Demo Boards and Development Kits DESCRIPTION Development Kit ISM Repeater Demo Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide Si4220/21 Universal ISM Band FSK Transmitters Si4320 Universal ISM Band FSK Receiver Note: Volume orders must include chip revision to be accepted ...