mmdoe28gxmsp-0va Samsung Semiconductor, Inc., mmdoe28gxmsp-0va Datasheet
mmdoe28gxmsp-0va
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mmdoe28gxmsp-0va Summary of contents
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA SAMSUNG PM410 SSD 1.8" LIF 128/64GB INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA SATA 1.5Gbps Document Title 1.8" SATA 3.0Gb/s LIF MLC SSD Revision History Revision No 0.1 Preliminary version 1.0 Final History 2 Final Revised Date Remark May. 23, 2008 Preliminary Nov. 10, 2008 Final Revision 1.0 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA Table of Contents 1.0 1.8" SATA 3.0Gb/s LIF General Description............................................................................................................... 5 2.0 Mechanical Specifications .......................................................................................................................................... 6 2.1 Physical dimensions and weight ................................................................................................................................ 6 3.0 Product Specifications ................................................................................................................................................ 7 3.1 System Interface and Configuration........................................................................................................................... 7 3.2 System Performance.................................................................................................................................................. 7 3.3 Drive Capacity............................................................................................................................................................ 7 3.4 Supply Voltage ........................................................................................................................................................... 7 3.5 System Power Consumption...................................................................................................................................... 7 3.6 System Reliability....................................................................................................................................................... 8 3.7 Environmental Specifications ..................................................................................................................................... 8 4.0 Electrical Interface Specification................................................................................................................................. 8 4.1 Serial ATA Interface connector .................................................................................................................................. 8 4 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA Table of Contents 7.3.1.11 S.M.A.R.T. Return Status (subcommand DAh) .............................................................................................. 23 7.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh) .............................................................. 23 7.3.2 Device Attribute Data Structure............................................................................................................................ 24 7.3.2.1 Data Structure Revision Number .................................................................................................................... 24 7.3.2.2 Individual Attribute Data Structure .................................................................................................................. 25 7.3.2.3 Off-Line Data Collection Status ...................................................................................................................... 26 7.3.2.4 Self-test execution status................................................................................................................................ 26 7.3.2.5 Total time in seconds to complete off-line data collection activity .................................................................. 26 7.3.2.6 Current segment pointer ................................................................................................................................. 26 7 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 1.0 1.8" SATA 3.0Gb/s LIF General Description The NSSD(Nand based Solid State Disk) of Samsung Electronics is fully consist of semiconductor device and using NAND Flash Memory which has a high reliability and a high technology for a storage media. As the NSSD doesn't have a moving parts such as platter(disk) and head media, it gives a good solution in a notebook PC and Tablet PC for a storage device with a high performance and a low power consumption and a small form factor ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 2.0 Mechanical Specifications 2.1 Physical dimensions and weight Physical dimensions and Weight Model Height (mm) MMDOE28GXMSP-0VA 5.0 -/+ 0.35 MMCRE64GXMSP-0VA 5.0 -/+ 0.35 Pin #1 Pin #1 Width (mm) 54.00 -/+ 0.20 71.0 -/+0.30 54.00 -/+ 0.20 71.0 -/+0.30 Pin #1 Pin #1 Figure 2-1. Physical dimension 6 Final Length (mm) Weigth (gram) 44.0 39.0 Revision 1.0 ...
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... Megabyte (MB Million bytes; 1 Gigabyte (GB Billion bytes 3.4 Supply Voltage Item Allowable voltage Allowable noise/ripple 3.5 System Power Consumption Power Read / Write Idle Standby Sleep MMCRE64GXMSP-0VA 64 GB 125,045,424 512 Bytes 7 Final (IOmeter @128KB, 128GB) Performance 90 MB/s 70 MB/s MMDOE28GXMSP-0VA 128 GB 250,069,680 Requirements 3. 100mV p-p or less (128GB, DIPM Enabled) Typical(W) 0.42 / 0.42 0.14 0.13 0.13 Revision 1.0 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 3.6 System Reliability MTBF 3.7 Environmental Specifications Features Temperature Humidity Vibration Shock 4.0 Electrical Interface Specification 4.1 Serial ATA Interface connector Drive Connector : DDK FF35-xxA-R11B 1000,000 Hours Operating 0°℃ to 70°℃ 95%, non-condensing 20G Peak, 10~2000Hz (15mins/Axis)x3 Axis 1500G, duration 0.5ms, Half Sine Wave ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 4.2 Pin Assignments No. 1 GND 2 3.3V 3.3V Power 3 3.3V 4 GND 5 5V 5.0V Power (*Not used GND 8 DAS Device Active Signal 9 GND 10 GND 11 A+ Differential Signal Pair Differential Signal Pair A 13 GND 14 B- Differential Signal Pair Differential Signal Pair B 16 GND ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 5.0 Frame Information Structure (FIS) 5.1 Register - Host to Device Table 5-1. Register - Host to Device layout (48bit LBA mode, EXT commands, NCQ commands) Table 5-2. Register - Host to Device layout (CHS mode) Table 5-3. Register - Host to Device layout (28bit LBA mode) 10 Final Revision 1.0 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 5.2 Register - Device to Host Table 5-4. Register - Device to Host layout (48bit LBA mode) Table 5-5. Register - Device to Host layout (CHS mode) Table 5-6. Register - Device to Host layout (28bit LBA mode) 11 Final Revision 1.0 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 5.3 Data 5.4 PIO Setup Table 5-8. Register - PIO Setup layout (48bit LBA mode: Read/Write Sector EXT) Table 5-9. PIO Set up layout (CHS mode: Commands include PIO data transfer) Table 5-7. Register - Data FIS layout 12 Final Revision 1.0 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 5.5 DMA Activate - Device to Host Table 5-10. DMA Activate Layout (Write DMA/Write DMA Queued/Service) 5.6 DMA Setup Table 5-11. DMA Setup layout (NCQ, Read/Write FpDMA Queued) 5.7 Set Device Bits - Device to Host Table 5-12. Set Device Bits layout (NCQ, Result of Read/Write FpDMA Queued commands) 13 Final ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 6.0 Shadow Register Block registers Description 6.1 Command Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. All other registers required for the command must be set up before writing the Command Register. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 6.4 Error Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. All other registers required for the command must be set up before writing the Command Register. 6.4.1 Field / bit description 7 6 ICRC UNC • ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 6.10 Status Register This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.0 Command Descriptions 7.1 Supported ATA Commands Command Name CHECK POWER MODE DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION RESTORE DEVICE CONFIGURATION SET DOWNLOAD MICROCODE EXECUTE DEVICE DIAGNOSTIC FLUSH CACHE FLUSH CACHE EXT IDENTIFY DEVICE IDLE IDLE IMMEDIATE INITIALIZE DEVICE PARAMETERS ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.2 SECURITY FEATURE Set The Security mode features allow the host to implement a securtity password system to prevent unauthorized access to the disk drive. 7.2.1 SECURITY mode default setting The NSSD is shipped with master password set to 20h value(ASCII blanks) and the lock function disabled. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the S.M.A.R.T. Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h) This subcommand causes the device to immediately initiate the set of activities that collect Attribute data in an offline mode (off-line routine) or execute a self-test routine in either captive or off-line mode. The LBA Low register shall be set to specify the operation to be executed. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.1.6 S.M.A.R.T. Selective self-test routine When the value in the LBA Low register 132, the Selective self-test routine shall be performed. This selftest routine shall include the ini- tial tests performed by the Extended self-test routine plus a selectable read scan. The host shall not write the Selective self-test log while the execution of a Selective self-test command is in progress ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h) This command returns the indicated log sector contents to the host. Sector count sepcifies the number of sectors to be read from the specified log. The log transfferred by the drive shall start at the first sector in the speicified log, regardless of the sector count requested. Sector nubmer indicates the log sector to be returned as described in the following Table ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.1.11 S.M.A.R.T. Return Status (subcommand DAh) This subcommand is used to communicate the reliability status of the device to the host's request. Upon receipt of the S.M.A.R.T. Return Sta- tus subcommand the device asserts BSY, saves any updated Attribute Values to the reserved sector, and compares the updated Attribute Val- ues to the Attribute Thresholds ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. Byte 0~1 Data structure revision number 2~361 1st - 30th Individual attribute data ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Byte 0 Attribute ID number 01-FFh Status flag bit 0 (pre-failure/advisory bit) bit attribute value is less than the threshold, the drive is in advisory condtion. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.2.3 Off-Line Data Collection Status The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates an Automatic Off-line Data Collection Sta- tus. Bit 7 Automatic Off-line Data Collection Status 0 Automatic Off-line Data Collection is disabled. 1 Automatic Off-line Data Collection is enabled. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.2.7 Off-line data collection capability Bit Definition 0 Execute Off-line Immediate implemented bit 0 S.M.A.R.T. Execute Off-line Immediate subcommand is not implemented 1 S.M.A.R.T. Execute Off-line Immediate subcommand is implemented 1 Enable/disable Automatic Off-line implemented bit 0 S.M.A.R.T. Enable/disable Automatic Off-line subcommand is not implemented 1 S.M.A.R.T. Enable/disable Automatic Off-line subcommand is implemented 2 Abort/restart off-line by host bit ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.3 Device Attribute Thresholds data structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All multibyte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte ordering, that is, that the least significant byte occupies the lowest numbered byte address location in the field ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.4 S.M.A.R.T. Log Directory The following defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Directory is on S.M.A.R.T. Log Address zero and is defined as one sector long. Byte 0~1 S.M.A.R.T. Logging Version 2 Number of sectors in the log at log address 1 3 Reserved 4 Number of sectors in the log at log address 2 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.5.4 Error log data structure The data format of each error log structure is shown below. Byte n ~ n+11 1st command data structure n+12 ~ n+23 2nd command data structure n+24 ~ n+35 3rd command data structure n+36 ~ n+47 4th command data structure n+48 ~ n+59 5th command data structure n+60 ~ n+89 Error data structure 7.3.5.5 Command data structure Data format of each command data structure is shown below ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.5.6 Error data structure Data format of error data structure is shown below. Byte n Reserved n+1 Content written to the Error register after command completion occurred. n+2 Content written to the Sector Count register after command completion occurred. n+3 Content written to the LBA Low register after command completion occurred. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.6 Self-test log structure The following defines the 512 bytes that make up the Self-test log sector. Byte 0~1 Data structure revision n*24+2 Self-test number n*24+3 Self-test execution status n*24+4~n*24+5 Life timestamp n*24+6 Self-test failure check point n*24+7~n*24+10 LBA of first failure n*24+11~n*24+25 Vendor specific ... ... 506~507 Vendor specific 508 ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 7.3.8 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Error condition A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the LBA High and LBA Mid registers. ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 8.2 Phy Power State 8.2.1 COMRESET sequence state diagram 8.2.2 Interface Power States 8.2.2.1 PHYRDY The Phy logic and main PLL are both on and active. The interface is synchronized and capable of receiving and sending data. 8.2.2.2 Partial The Phy logic is powered, but reduced power state. Both signal lines on the interface are at a neutral logic state (common mode volt- age) ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 8.2.4 PHYRDY to Partial/Slumber 8.2.4.1 Host Initiated for Partial 8.2.4.2 Device Initiated for Partial *For Slumber, the same sequence applies except PMREQ_PP is replaced with PMREQ_SP and Partial is replaced with Slumber. 9.0 SATA II Optional Feature 9.1 Power Segment Pin 8 Pin 8 of the power segment of the device connector may be used by the device to provide the host with an activity indication and it may be used by the host to indicate whether staggered spinup should be used ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 9.2 Activity LED indication The signal provides for activity indication is a low-voltage low-current driver intended for efficient integration into present and future IC manu- facturing processes. The signal is NOT suitable for directly driving an LED and must first be buffered using a circuit external to the drive before driving an LED ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 10.0 Identify Device Data Word 64GB/128GB 0 0040h General information 1 3FFFh Number of logical cylinders 2 C837h Specific configuration 3 0010h Number of logical heads Retired 6 003Fh Number of logical sectors per logical track Reserved 9 0000h Retired 10 -19 XXXX Serial number(20 ASCII characters ...
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... MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA Word 64GB/128GB 86 3C01h Command set/feature enabled 87 4023h Command set/feature default 88 203Fh Ultra DMA transfer 89 0003h Time required for security erase unit completion 90 0003h Time required for Enhanced security erase complete 91 0000h Current advanced power management value 92 FFFEh Master Password Revision Code ...
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... CR : 64G DO: 128G 5. Feature E : NSSD 6~8. NSSD Density 64G : 64G Byte 28G : 128G Byte 9. NSSD Type X : 1.8" LIF Formfator 10. Component Generation M 12.0 Product Line up Part Number MMCRE64GXMSP-0VA MMDOE28GXMSP-0VA 11. Flash Package S 12. PCB Revision AND Production Site P 13. " ...