dg221 ETC-unknow, dg221 Datasheet - Page 4
dg221
Manufacturer Part Number
dg221
Description
Quad Spst Cmos Analog Switch With Latches
Manufacturer
ETC-unknow
Datasheet
1.DG221.pdf
(6 pages)
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Test Circuits
2 V
DG221
4
2 V
S
IN
S
IN
GND
GND
WR
C
C
L
L
0 V
(includes fixture and stray capacitance)
(includes fixture and stray capacitance)
+15 V
WR
V+
V
V
O
The latches are level sensitive. When WR is held low the latches are transparent and the switches
respond to the digital inputs. The digital inputs are latched on the rising edge of WR.
O
= V
= V
+15 V
–15 V
–15 V
V+
V–
V–
S
S
D
D
R
R
L
L
R
+ r
R
R
1 k
+ r
R
1 k
L
L
L
L
DS(on)
DS(on)
VOUT
WR
3 V
3 V
IN
C
35 pF
C
35 pF
Figure 4. WR Setup Conditions
L
Figure 3. WR Switching Time
L
Figure 2. Switching Time
V
V
O
O
50%
t
S
t
H
50%
V
WR
OUT
IN
Switch
Switch
Output
Logic
Input
Input
t
ON
t
V
S
3 V
0 V
3 V
0 V
V
O
, WR
t
S
W
V
3 V
0 V
V
O
t
S
H
50%
S-52881—Rev. C, 28-Apr-97
t
ON
50%
90%
t
t
t
H
S
W
= Setup Time
= Hold Time
= WR Pulse Width
90%
t
t
r
f
< 10 ns
< 10 ns
t
OFF
Siliconix
t
t
r
f
t
OFF
< 10 ns
< 10 ns
, WR