t71l6808a TM Technology Inc., t71l6808a Datasheet
t71l6808a
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t71l6808a Summary of contents
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... TE CH The T71L6808A is an octal-port 10/100Mbps dual speed Ethernet switch integrated both with an embedded SSRAM and a 1K entries of address table. A high performance Fast Ethernet switch, fully complies with the IEEE802.3, 802.3u and 802.3x specifications, can be implemented using the T71L6808A with physical devices. The T71L6808A is intended for applications to stand-alone switch for low-cost SOHO market ...
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... VLAN group will not affect the activities in other VLAN group. The two groups of four ports are suitable for SOHO application at two different working groups. The T71L6808A also supports trunking applications. With trunking possible to group up to two full-duplex links together to form a single 400 Mbit/s link. ...
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... TE CH System Diagram Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 3 Publication Date:May. 2001 Revision:0.A ...
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... RMII Interface The T71L6808A provides 10/100 Mbps low pin count RMII interface for use between PHY and T71L6808A. The RMII is capable of supporting 10Mbps and 100Mbps data rates. A single clock reference, 50MHz, sourced from an external clock input is used for receive and transmit. It also provides independent 2 bit wide (di-bit) transmit and receive data paths ...
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... The data reception port will go into the receive-state when CRS in the RMII interface is asserted. The RMII (Reduced Media Independent Interface) presents the received data in two-bit (di-bit) that are synchronous to the RMII reference clock (50 MHz). The T71L6808A will then attempt to detect the occurrence of the SFD (Start Frame Delimiter) pattern “10101011.” All preamble data prior to SFD are discarded ...
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... If the SA was not found in the address table(a new address), the T71L6808A waits until the end of the packet (no-error packet) and updates the address table. If the SA was found in the address table, then aging value of each corresponding entry will be reset to 0 ...
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... The T71L6808A supports IEEE 802.3x full duplex flow control and half duplex back pressure congestion control. The IEEE 802.3x flow control's ability is auto-negotiated between remote device and the T71L6808A by writing the flow control ability via MDIO to external connected PHY. The T71L6808A adopts a special back-pressure design, forwarding one packet successfully after 28 force collisions, to avoid the connected repeater being partitioned ...
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... The trunking algorithm determines on which of these ports a frame is transmitted so that the load is spread across these ports. However, while traffic should be shared between trunking ports as evenly as possible. The T71L6808A supports port 0 and port one trunk group. Hense, the maximum aggregated bandwidth for trunking group is 400Mbps. (or ...
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... Interface The 24LC02 interface is a 2-wire serial EEPROM interface providing 2K bits storage space. After power on reset, the T71L6808A uses Random Read and Sequential Read commands to auto-load configuration settings, pause frame source address and so on. After auto-loaded, the 24LC02 interface pins SCL and SDA are tri-stated for on-line updating 24LC02 contents through a parallel port ...
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... Random Read: A random read requires a "dummy" byte write sequence to load in the data word address. Sequential Read: For T71L6808A, the sequential reads are initiated by a random address read. After the 24LC02 receives a data word, it responds with an acknowledge. As long as the 24LC02 receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words ...
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... TE CH Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 11 Publication Date:May. 2001 Revision:0.A ...
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... TE CH Pin Assignment Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 12 Publication Date:May. 2001 Revision:0.A ...
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... I 53 SYSCLK I 119 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A Pin Description Function Reference Clock. REFCLK is a 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN and TXD[1:0]. Transmit Data. TXD[1:0] shall transition synchronously with respect to REFCLK ...
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... ARL_PAIR I 125 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A Management Interface (MI) Clock Output. This MI clock shifts serial data in and out of MDIO on rising edges from an external Physical Layer device. Management Interface (MI) Data I/O. This bi-directional pin contains serial data that is clocked in and out on rising edges of the MDC clock from an external Physical Layer device ...
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... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A Test Pin. For internal use. Must be tied to ground for normal use. Test Pin. For internal use. Must be tied to ground for normal use. Test Pin. For internal use. Must be tied to ground for normal use. ...
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... SnoopEn: When 0, snooping disable. When 1, snooping enable. MPID[2:0]: Monitored Port ID. SPID[2:0]: Snooping Port ID for incoming frame flow. Note : All 0-fields must be filled with 0. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A ...
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... Maximum Low Level Input Voltage IL I Input Current IN I Tri-State Output Leakage Current OZ I Average Operating Supply Current CC Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A Minimum Maximum -55 +125 0 70 Conditions Minimum Typical Maximum Unit =-8mA 0. =8mA OL 0 ...
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... Characteristics Reset and Clock Timing Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 18 Publication Date:May. 2001 Revision:0.A ...
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... TE CH RMII Timing Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 19 Publication Date:May. 2001 Revision:0.A ...
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... TE CH PHY Management Timing Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 20 Publication Date:May. 2001 Revision:0.A ...
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... TE CH Serial EEPROM 24LC02 Timing Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 21 Publication Date:May. 2001 Revision:0.A ...
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... package Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 22 Publication Date:May. 2001 Revision:0.A ...
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... TE CH Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T71L6808A P. 23 Publication Date:May. 2001 Revision:0.A ...