ad6437 Analog Devices, Inc., ad6437 Datasheet - Page 7

• Manufacturer Part Number: ad6437
• Description: Analog Front End For Adsl
• Manufacturer: Analog Devices, Inc.

This Material Copyrighted By Its Respective Manufacturer
Register
REG A
REG B
REG C
REG D
NA = Not Assigned.
ANCILLARY AND SUPPORT SECTION
Auxiliary D/A
There is a 7-bit monotonic DAC, with an output buffer, that
can be used for system control. Typically, this will be used for
timing recovery, to drive a VCXO.
The output buffer load must be greater than 100 k .
DIGITAL INTERFACE TO AD6437
The digital I/O pins can interface to either 3.3 V or 5 V logic.
The voltage connected to the DVDD_3 V power pins (Pins 3
and 72) determines the interface voltage. Although the DVDD_3 V
pins can be connected to either 3.3 V or 5 V, they must be con-
nected to the same voltage. When interfacing to the other chips
in the ADSL system, the AD6437 DVDD_3 V power pins should
ideally be connected to 3.3 V; in addition to lower power con-
sumption, this lowers board noise and digital feedthrough into
the AD6437 data converters.
DVDD_5 V must always be connected to 5 V.
See the Digital Interface section of the electrical specifications in
the AD6437 data sheet for details on minimum and maximum
logic levels.
REV. 0
Pin Name
SDATA
SFRAME
SCLK
PGA Control
Power Mode
Aux DAC Data
Control
Name
Pg[5:0]
lpchip
pdpgaaa
pdtxfil
pdtrdac
pd12dac
trd[6:0]
alpbk
aafbp
txfsel
Data Transmit
Transmit Frame Sync
Definition
Serial Clock
Field
Reg A
Reg B[4]
Reg B[3]
Reg B[2]
Reg B[1]
Reg B[0]
Reg C
Reg D[2]
Reg D[1]
Reg D[0]
Bit 7
NA
NA
NA
test1
Description
Programmable Gain Amplifier Gain Bits. Pg 0 LSB. See Table I.
Low Power Mode. Powers down all chips except ADC. Active High.
Power-Down Receive PGA and AA Filter. Active High.
Power-Down Transmit Filters. Active High.
Power-Down Timing Recovery DAC. Active High.
Power-Down 12-Bit DAC. Active High.
Timing Recovery DAC Data; trd0 LSB, Data Format Binary.
Analog Loop Back. Active High.
AA Filter Bypass. Active High. Powers down the filter.
Transmit Filter Select. txfsel = 0, 138 kHz, txfsel = 1, 1 MHz Filter Select.
Table IV. Register Bit Field Function
Table II. AD6437 Serial Port I/O
Bit 6
NA
NA
trd6
NA
Table III. Register Function
Input
Input
Input
Type
Bit 5
Pg 5
NA
trd5
NA
–7–
Description
Data Output from Host Processor (e.g., ADSP-2183)
Sync Output from Host Processor
Clock Output from Host Processor
SERIAL INTERFACE
The serial port interface has the ability to interface with most
digital systems (e.g., the ADSP-2183 used in the Analog
Devices ADSL chipsets).
The interface consists of three signals: SDATA, SCLK and
SFRAME (described in Table II and Figure 6). The SDATA
and SFRAME are clocked into the DSP Interface block on a
falling edge of SCLK. The DSP interface decodes the first three
bits of the incoming data word to determine if the AD6437 is
being addressed. If the DSP has selected the AD6437, the next
10 bits are accepted. The first two bits decode one of four inter-
nal data registers (Reg A, Reg B, Reg C, and Reg D), and the
following eight bits used as data to be loaded into that register.
NOTE: The AD6437 registers may not start up in a defined
state on power-up. They should be cleared to explicitly set them
to a known state before use.
Bit 4
Pg 4
lpchip
trd4
test
Bit 3
Pg 3
pdpgaaa
trd3
NA
Bit 2
Pg 2
pdtxfil
trd2
alpbk
Pg 1
trd1
aafbp
Bit 1
pdtrdac
AD6437
Bit 0
Pg 0
pd12dac
trd0
txfsel