ad6437 Analog Devices, Inc., ad6437 Datasheet - Page 8

• Manufacturer Part Number: ad6437
• Description: Analog Front End For Adsl
• Manufacturer: Analog Devices, Inc.

This Material Copyrighted By Its Respective Manufacturer
AD6437
TIMING
RECEIVE INTERFACE
The analog input is sampled every the rising edge of the ADC clock (RX_CLK), with digital data (RX11:RX0) being valid on each
falling edge of RX_CLK. Due to the pipeline architecture used in the ADC, there is a three-cycle latency in the receive data as shown
in the diagram.
SDATA [2:0]
Determines if AD6437 is selected,
Addr 101 is assigned for AD6437.
NOTE
Data is transmitted in 13-bit words: SDATA 0, LSB, transmitted first; SDATA 12, MSB, transmitted last.
Symbol
t
t
t
t
Latency
C
CH
CL
OD
ANALOG INPUT
OUTPUT DATA
INPUT CLOCK
TX[13:0]
TXCLK
RX[0:11]
RCVCK
Parameter
Clock Period
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay
Figure 5. Receive Interface Timing Diagram
Table VII. Receive Switching Specifications
Symbol
t
t
t
Figure 4. Transmit DAC Data Timing
Table V. Serial Interface Data Format
S
H
LPW
S1
Table VI. Transmit DAC Timing
t
CH
t
SDATA [3:4]
Selects AD6437 register.
SDATA [4
C
Min
12
12
16
t
t
S
CL
S2
–8–
Typ Max
0
0
1
1
t
0 Reg A
1 Reg B
0 Reg C
1 Reg D
H
3]
Min
45
45
8
3
S3
t
LPW
Units
ns
ns
ns
Typ
100
13
3
SDATA [5:12]
Data byte written (LSB first).
SDATA 12, MSB
SDATA 5, LSB
t
OD
S4
Max
19
3
DATA1
Units
ns
ns
ns
ns
Cycles
REV. 0