ad6437 Analog Devices, Inc., ad6437 Datasheet - Page 9

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ad6437

Manufacturer Part Number
ad6437
Description
Analog Front End For Adsl
Manufacturer
Analog Devices, Inc.
Datasheet

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This Material Copyrighted By Its Respective Manufacturer
Typical 6.6 MHz synchronous control interface rate.
CONNECTION AND APPLICATION INFORMATION
Decoupling
All the internal bias points of the AD6437 DAC and ADC are decoupled as shown in Figures 2 and 3. All AD6437 power pins should
be decoupled with a 10 F tantalum capacitor and a parallel 0.1 F ceramic chip cap. The 0.1 F capacitors should be placed
as closely as possible to the device pins. This configuration ensures a low impedance power source over a wide band of frequencies.
REV. 0
Symbol
t
t
t
t
t
SCLKW
RD
RH
SCDV
SCDH
SIMPLEX DATA
DUPLEX DATA
External Clock
Switching Characteristics
Clock Period (6.6 MHz)
SFRAME Delay After SCLK
SFRAME Hold After SCLK
SCLK High to SDATA Valid (Delayed)
Transmit Data Hold After SCLK
SDATA_IN
MESSAGES
SFRAME
CONTROL
SCLK
(INTERLEAVE)
TO RAM
Table VIII. Serial Port Interface Timing Parameters
AD6435
(DTIR)
DRIVE
EDGE
Figure 7. Example System Configuration
Figure 6. Serial Port Interface Timing
t
RD
ADSP-2183
t
AD6436
SCLKW
(DME)
t
SCDV
TO BOOT EPROM
–9–
(AD6437)
BUFFER
AD6437
AD826
t
RH
SAMPLE
Typ
151
EDGE
AD8042
VALID DATA
(BPF)
Min
0
0
RECEIVER)
(DRIVER/
HYBRID
AD816
Max
15
15
t
SCDH
TO LINE
AND POTS
SPLITTER
Units
ns
ns
ns
ns
ns
AD6437

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