isl54220 Intersil Corporation, isl54220 Datasheet
isl54220
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isl54220 Summary of contents
Page 1
... USB host (computer). The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54220 has an output enable pin to open all the switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. The ISL54220 is available 1.8mmx1.4mm µ ...
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... ISL54220IRTZ (Note 3) 4220 ISL54220IRTZ-T* (Note 3) 4220 ISL54220IUZ (Note 3) 54220 ISL54220IUZ-T* (Note 3) 54220 ISL54220IRUEVAL1Z Evaluation Board *Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Turn-OFF Time 3.3V, R OFF DD 3 ISL54220 Thermal Information Thermal Resistance (Typical µTQFN Package (Note TDFN Package (Notes 6, 7 0.3V MSOP Package (Note Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40° ...
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... ON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. 13. Limits established by characterization and are not production tested. 4 ISL54220 Test Conditions +3.3V, GND = 0V 1.4V 0.5V, (Note 8), Unless Otherwise Specified. (Continued) ...
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... Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS VDD LOGIC INPUT 0V SWITCH OUTPUT V OUT 0V FIGURE 2A. MEASUREMENT POINTS V Repeat test for all switches. 5 ISL54220 t < 20ns r t < 20ns f SWITCH INPUT OUT 90% Repeat test for all switches. C capacitance. FIGURE 1. SWITCHING TIMES V INPUT ...
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... OUT+ t skew_o OUT- 50% 90% 10 FIGURE 6A. MEASUREMENT POINTS 6 ISL54220 (Continued SIGNAL GENERATOR SEL 0V OR VDD OE ANALYZER Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. VIN 15.8Ω DIN+ 15.8Ω DIN- |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals ...
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... V more than -0.3V for normal operation. However, in the event that the USB 5.25V V shorted to one or both of the D-/D+ pins, the ISL54220 has special fault protection circuitry to prevent damage to the ISL54220 part. The fault circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D driven up to 5.5V while the V this condition the part draws < ...
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... The USB specification in section 7.1.1 states a USB device must be able to withstand a V signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54220 part has special fault protection circuitry to meet these short circuit requirements. The fault protection circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D driven ...
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... V (V) COM FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE 9 ISL54220 Any components connected on the active channel must be able to withstand the overvoltage condition. Note: During the fault condition normal operation of the USB channel is not guaranteed until the fault condition is BUS removed +25°C, Unless Otherwise Specified ...
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... Typical Performance Curves V = 3.3V DD FIGURE 11. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH 10 ISL54220 T = +25°C, Unless Otherwise Specified (Continued) A TIME SCALE (0.2ns/DIV) FN6819.0 December 16, 2008 ...
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... FIGURE 12. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH 50Ω 0dBm, 0.2VDC BIAS IN 1M 10M FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE 11 ISL54220 T = +25°C, Unless Otherwise Specified (Continued) A TIME SCALE (10ns/DIV) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 100M 1G ...
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... L - 0dBm, 0.2VDC BIAS IN -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001 0.01 0.1 1M FREQUENCY (Hz) FIGURE 15. CROSSTALK 12 ISL54220 T = +25°C, Unless Otherwise Specified (Continued) A Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 325 PROCESS: Submicron CMOS 10M 100M 500M FN6819.0 December 16, 2008 ...
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... NX L PIN # BOTTOM VIEW C L (A1) NX (b) 5 SECTION "C-C" 2.20 1.00 1.00 0.60 0.50 1.80 0.20 0.40 10 LAND PATTERN 13 ISL54220 L10.1.8x1. LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE E SYMBOL 10X θ 0. ...
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... B - 10. Datums -A - and to be determined at Datum plane . - H - 11. Controlling dimension: MILLIMETER. Converted inch dimen- sions are for reference only 14 ISL54220 M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE SYMBOL θ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 ISL54220 L10.3x3A 0.10 C ...