isl88731a Intersil Corporation, isl88731a Datasheet - Page 11

• Manufacturer Part Number: isl88731a
• Description: Smbus Level 2 Battery Charger
• Manufacturer: Intersil Corporation

The System Management Bus
The System Management Bus (SMBus) is a 2-wire bus that
supports bidirectional communications. The protocol is
described briefly here. More detail is available from
www.smbus.org.
General SMBus Architecture
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 16.
SDA
SCL
CPU
SMBUS MASTER
CONTROL
CONTROL
SDA
SCL
DATA VALID
DATA LINE
OUTPUT
INPUT
OUTPUT
INPUT
STABLE
FIGURE 16. DATA VALIDITY
VDDSMB
ALLOWED
SLAVE DEVICES
CHANGE
OF DATA
TO OTHER
11
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
CONTROL
CONTROL
CONTROL
CONTROL
SMBUS SLAVE
SMBUS SLAVE
SCL
SDA
SCL
SDA
REGISTERS,
REGISTERS,
MACHINE,
MACHINE,
MEMORY,
MEMORY ,
STATE
STATE
ETC
ETC
ISL88731A
START
SDA
SCL
START and STOP Conditions
As shown in Figure 17, START condition is a HIGH-to-LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW-to-HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
Acknowledge
Each address and data transmission uses 9-clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7-slave address bits and a R/W bit
during the next 8-clock pulses. During the ninth clock pulse, the
device that recognizes its own address holds the data line low
to acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data (see Figure 18).
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address (0001001 for the
ISL88731A) followed by the R/W bit. The R/W bit is 0 for a write
or 1 for a read. If any slave devices on the SMBus bus
recognize their address, they will Acknowledge by pulling the
serial data (SDA) line low for the last clock cycle in the control
byte. If no slaves exist at that address or are not ready to
communicate, the data line will be 1, indicating a Not
Acknowledge condition.
Once the control byte is sent, and the ISL88731A
acknowledges it, the 2nd byte sent by the master must be a
register address byte such as 0x14 for the ChargeCurrent
register. The register address byte tells the ISL88731A
which register the master will write or read. See Table 1 for
details of the registers. Once the ISL88731A receives a
register address byte it responds with an acknowledge.
SDA
SCL
CONDITION
START
FIGURE 18. ACKNOWLEDGE ON THE I
S
FIGURE 17. START AND STOP WAVEFORMS
MSB
1
2
8
2
C BUS
ACKNOWLEDGE
FROM SLAVE
CONDITION
January 7, 2009
STOP
P
9
FN6738.1