isl6262a Intersil Corporation, isl6262a Datasheet
isl6262a
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isl6262a Summary of contents
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... Pb-Free (RoHS Compliant) Ordering Information PART NUMBER (Note) ISL6262ACRZ ISL6262ACRZ-T* ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7 ISL6262AIRZ ISL6262AIRZ-T* ISL6262 AIRZ *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and ...
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... Pinout 1 PGOOD 2 PSI# 3 PMON 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 2 ISL6262A ISL6262A (48 LD 7x7 QFN) TOP VIEW GND PAD (BOTTOM BOOT1 35 UGATE1 34 PHASE1 33 PGND1 32 LGATE1 31 PVCC ...
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... Droop Amplifier Offset R Voltage BIAS Boot Voltage Maximum Output Voltage VID Off State 3 ISL6262A Thermal Information Thermal Resistance (Typical) QFN Package (Notes 1, 2 Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C -0.3V to +9V (<10ns) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www ...
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... I LGATE Sink Resistance R LGATE Sink Current I UGATE to PHASE Resistance GATE DRIVER SWITCHING TIMING (refer to “ISL6262A Gate Driver Timing Diagram” on page 6) UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-on Propagation Delay LGATE Turn-on Propagation Delay ...
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... PMON Sinking Current Maximum Current Sinking Capability PMON Impedance CLK_EN# OUTPUT LEVELS CLK_EN# High Output Voltage CLK_EN# Low Output Voltage 5 ISL6262A = -40°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% A SYMBOL TEST CONDITIONS t CLK_EN# Low to PGOOD High ...
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... ISL6262A Gate Driver Timing Diagram PWM t PDHU UGATE 1V LGATE t FL Functional Pin Description PGOOD 1 PSI PMON 4 RBIAS VR_TT NTC 7 SOFT 8 OCSET VW 9 COMP FB2 12 6 ISL6262A PDHL GND PAD (BOTTOM ...
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... GND - Signal ground. Connect to local controller ground. VDD - 5V control power supply. ISEN2 - Individual current sharing sensing for Channel 2. If ISEN2 is pulled to 5V, phase 2’s gate signals are disabled. ISL6262A is then configured in always-1-phase mode. 7 ISL6262A ISEN1 - Individual current sharing sensing for Channel 1. ...
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... ISEN2 CURRENT BALANCE ISEN1 3V3 PGOOD PGOOD MONITOR CLK_EN# AND LOGIC P FLT GOOD FAULT AND PGOOD LOGIC RBIAS DAC FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6262A 8 ISL6262A PVCC PVCC PVCC 1.24V DRIVER LOGIC ULTRA- SONIC TIMER FLT VSOFT VSOFT I_BALF VIN VIN ...
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... FIGURE 4. ACTIVE MODE EFFICIENCY, 1 PHASE, CCM, PSI# = LOW, VID = 1.15V 100 8. 12. 19. 0.1 1.0 I (A) OUT FIGURE 6. DEEPER SLEEP MODE EFFICIENCY 9 ISL6262A 300kHz Operation, 2xIRF7821 as Upper Devices and 2xIRF7832 as Bottom Devices 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1. FIGURE 3. ACTIVE MODE LOAD LINE, 2 PHASE, CCM, 1.16 1.15 1.14 1.13 1.12 1.11 1.10 12 ...
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... OUT FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE 240µ ISL6262A 0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps V OUT C = 15nF SOFT FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE = 10A LOAD IMVP-6+_PWRGD FIGURE 11. 2 PHASE CURRENT BALANCE, FULL LOAD (50A) LINE TRANSIENT FIGURE 13 ...
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... FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH VID LSB CHANGE, AT DPRSLPVR = 0, DPRSTP 10A LOAD 11 ISL6262A 0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued) LOAD TRANSIENT FIGURE 15. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V LOAD TRANSIENT FIGURE 17. VID3 CHANGE OF 010X000 FROM 1. FIGURE 19 ...
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... FIGURE 22. SLOW C4 EXIT WITH DELAY OF DPRSLPVR, FROM VID1000000 (0.7V) TO 0110000 (0.9V) V OUT PGOOD IL1, IL2 FIGURE 24. OVERCURRENT PROTECTION 12 ISL6262A 0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued) C4 ENTRY WITH PSI# ASSERTION FIGURE 21. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V V Vcore CORE FIGURE 23 ...
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... CURRENT SOURCING (mA) FIGURE 30. POWER MONITOR CURRENT SOURCING CAPABILITY 13 ISL6262A 0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued) PMON PMON = 21A, FIGURE 27. VID = 1.15V, LOAD TRANSIENT 36A LOAD Vcore V CORE FIGURE 29. VID = 1.15V, LOAD APPLICATION FROM 7Ω ...
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... IMVP-6+_PWRGD REMOTE SENSE FSET C 9 FIGURE 32. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING 14 ISL6262A 3V3 VDD PVCC VIN RBIAS NTC ISL6262A VR_TT# UGATE1 SOFT BOOT1 C 6 VIDs PHASE1 ...
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... IMVP-6+_PWRGD REMOTE SENSE FSET C 9 FIGURE 33. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING 15 ISL6262A 3V3 VDD PVCC VIN RBIAS ISL6262A NTC VR_TT# UGATE1 SOFT BOOT1 C 6 VIDs PHASE1 DPRSTP# ...
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... VID table value by an amount proportional to current to achieve the IMVP-6+ load line. The ISL6262A provides for current to be measured using either resistors in series with the channel inductors as shown in the application circuit of Figure 33, or using the intrinsic series resistance of the inductors as shown in the application circuit of Figure 32 ...
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... In this mode of operation, the lower MOSFET will be configured to automatically detect and prevent discharge current flowing from the output TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262A IN TWO-PHASE DESIGN DPRSLPVR DPRSTP# Intel IMVP-6+ ...
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... When PSI#, DPRSTP#, and DPRSLPVR are all asserted, the controller will transition to single-phase DCM mode. In this mode, both MOSFETs associated with phase 2 are off, and the ISL6262A turns off the lower MOSFET of Channel 1 whenever the Channel 1 current decays to zero. As load is further reduced, the phase 1 channel switching frequency decreases to maintain high efficiency ...
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... Component Selection and Application Soft-Start and Mode Change Slew Rates The ISL6262A uses two slew rates for various modes of operation. The first is a slow slew rate used to reduce in-rush current during start-up also used to reduce audible noise when entering or exiting Deeper Sleep Mode ...
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... GV CPU die is the correct level independent of load current. is SOFT The VSEN and RTN pins of the ISL6262A are connected to Kelvin sense leads at the die of the processor through the (EQ. 2) processor socket. These signal names are Vcc_sense and Vss_sense respectively. This allows the voltage regulator to ...
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... FSET For 300kHz operation suggested to be 6.81kΩ. In fset discontinuous conduction mode (DCM), the ISL6262A runs in period stretching mode. The switching frequency is dependent on the load current level. In general, the lighter load, the slower switching frequency. Therefore, the switching loss is much reduced for the light load operation, which is important for conserving the battery power in the portable application ...
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... T 1 273 + + e e – 22 ISL6262A For those cases where the constant b is not accurate enough to approximate the resistor value, the manufacturer provides the resistor ratio information at different temperatures. The nominal NTC resistor value may be expressed in another way shown in Equation 10. R NTCTo ...
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... Static Mode of Operation - Static Droop Using DCR Sensing As previously mentioned, the ISL6262A has an internal differential amplifier which provides for very accurate voltage regulation at the die of the processor. The load line regulation is also accurate for both two-phase and single-phase operation ...
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... NTC to the inductor. As only one NTC is required in this application, this NTC should be placed as close to the Channel 1 inductor as possible and 24 ISL6262A PCB traces sensing the inductor voltage should be going ) k • directly to the inductor pads. droopamp (EQ ...
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... ISL6262A uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6262A forces the ISEN voltages to be almost equal, the (EQ. 29) inductor currents will not be exactly equal. Using DCR current sensing as an example, two errors have to be added to find the total current imbalance ...
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... R desired droop value. Fault Protection - Overcurrent Fault Setting As previously described, the overcurrent protection of the ISL6262A is related to the droop voltage. Previously we have calculated that the droop voltage = ILoad*R where R droop in the Intel IMVP-6+ specification. Knowing this relationship, the overcurrent protection threshold can be set voltage droop level ...
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... OC + DROOP INTERNAL TO ISL6262A + VDIFF RTN VSEN FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
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... L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ISL6262A 4X 5.5 A 44X 0. 48X 0 . 40± BOTTOM VIEW ± SIDE VIEW ( 44X REF C ( 48X 0 ...