isl6590dr Intersil Corporation, isl6590dr Datasheet

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isl6590dr

Manufacturer Part Number
isl6590dr
Description
Digital Multi-phase Pwm Controller For Core-voltage Regulation
Manufacturer
Intersil Corporation
Datasheet
Digital Multi-Phase PWM Controller for
Core-Voltage Regulation
Processors that operate above a GHz require fast, intelligent
power systems. The Intersil ISL6590 controller offers
intelligent digital, multi-phase control that provides high
bandwidth, optimal control frequency response, noise
immunity and active transient response control algorithms.
The design is fully scalable for controlling up to six phases,
each featuring the Intersil ISL6580 intelligent power stage.
The user can configure and monitor the power system via
the Asynchronous Serial Interface (ASI). The ISL6590
controller flexibility can be extended with the addition of an
external EEPROM for updating key circuit operating
parameters in the control loop and overall system design.
The digital architecture reduces the design time for
engineers with the use of our software. The software allows
the designer the freedom to choose output stage
components and still achieve optimized system
performance.
The ISL6590 digital controller communicates with the
ISL6580 integrated power stages via 100% digital signaling.
Serial communication allows for separation of the controller
and the power stage, providing placement and layout
freedom to the power stage. The digital controller
implements phase balancing to ensure even distribution of
phase currents. The ISL6590 controller configures the
ISL6580 power stage current limit, VID reference, non-
overlap period, Active Transient Response (ATR) trigger
levels and maximum temperature limit. The digital controller
also monitors the ISL6580 power stage peak currents, over-
temperature fault, input under voltage, output over/under
voltage to ensure proper operation of the power supply.
Pinout
VDD_CORE
NDRIVE1
PWRGD
VDD_IO
OUTEN
VID [0]
VID [1]
VID [2]
VID [3]
VID [4]
VID [5]
PWM1
MCLK
MDO
MCS
MDI
01
16
64
17
ISL6590 (QFN)
TOP VIEW
®
1
Data Sheet
All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc.
49
32
48
33
TEST 2
ATRL
SOC
ERR
VDD_IO
SYS_CLK
VDD_IO
NC
NC
VDD_CORE
NC
NC
IDIG6
PWM6
NDRIVE6
TEST1
1-888-INTERSIL or 321-724-7143
CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Open Architecture features software programmable
• Intel VR10
• 250kHz to 1MHz switching frequency
• 100% digital control and signaling
• Active Transient Response (ATR) control algorithms for
• Controls up to six ISL6580 intelligent power stages (20A
• Programmable Adaptive voltage positioning (AVP) load
• Configurable control loop parameters (with optional
• Programmable MOSFET dead time control
• High speed voltage and current control loops
• PWRGD and OUTEN
• Serial interface to ISL6580 power stages for system
• 64 Ld 9x9 QFN package
• QFN Package Option
Ordering Information
ISL6590DR
control loop compensation enabling optimal system
performance
- User accessible asynchronous serial interface
- 6-bit Dynamic VID™
- Output voltage regulation range of 0.8375V to 1.600Vdc
minimized voltage droop and overshoot
per phase, 120A total system current)
line
external EEPROM)
monitoring and configuration
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
- QFN Near Chip Scale Package Footprint; Improves
PART NUMBER
Flat No Leads - Product Outline
PCB Efficiency, Thinner in Profile.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
April 2003
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
TEMP. (
0 to 85
o
C)
64 Ld 9x9 QFN L64.9x9-S
PACKAGE
ISL6590
FN9061
PKG. NO.

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isl6590dr Summary of contents

Page 1

... Ld 9x9 QFN package • QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile. Ordering Information PART NUMBER ISL6590DR 49 TEST 2 48 ATRL SOC ERR VDD_IO ...

Page 2

Typical Application Circuit 3.3 V 1.8 V VDD_IO VDD_CORE ERR SOC VID[0:5] SCLK SDATA PWRGD SYSCLK OUTEN PWM IDIG NDRIVE ARX ATX ISL6590 ATRH ATRL OSC_IN OSC_OUT PWM IDIG NDRIVE TEST1 TEST2 TEST3 TEST4 MDO MDI MCS MCLK PWM IDIG ...

Page 3

Absolute Maximum Ratings Supply Voltage (VDD_IO ...

Page 4

Electrical Specifications Operating Conditions: V PARAMETER POWER-ON RESET AND ENABLE POR Threshold OUTEN Threshold OUTEN Rising OUTEN Falling OSCILLATOR Adjustment Range Max Duty Cycle NOTE: 1. Reserved for note. Block Diagram Ext_Reset POR Asynchronous ATX Serial ...

Page 5

Pin Descriptions PIN NO. PIN NAME TYPE 1 OUTEN Input 2-7 VID[0:5] Input 8, 21, 39, 57 VDD_CORE Power 9 PWRGD Output 10, 25, 42, VDD_IO Power 44 MCLK Output 12 MDO Output 13 MDI Input 14 MCS ...

Page 6

General Description The ISL6590 is a multiphase digital controller optimized for microprocessor core voltage generation in the 0.8375Vdc - 1.600Vdc output range and high current loading up to 150A with a 12Vdc input intended to be used as ...

Page 7

OFFSET BINARY V ERR (FROM ERR SIGNAL - ISL6580 VOLTAGE ADC) 6-BIT SERIAL IDIG 1 IDIG 2 IDIG 3 IDIG 4 IDIG 5 IDIG 6 ISHARE ATRH ATRL (FROM ISL6580 ATRH AND ATRL SIGNALS) Block Diagram Details Feedback Control ...

Page 8

Voltage ADC (ISL6580) Each of the ISL6580s contain a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. The ...

Page 9

VID Map TABLE 1. VOLTAGE IDENTIFICATION (VID) V (V) VID5 VID4 VID3 OUT 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0 0 ...

Page 10

PID Feedback Control PID block not only performs each of the basic Proportional, Integral, and Differential compensation components, it also includes a Low Pass Filter (LPF) to help reduce high frequency noise and a transient recovery path to help transient ...

Page 11

Non- Volatile Memory map. FIGURE 4. EEPROM DATA READ TIMING TABLE 6. EEPROM DATA READ TIMING TIMING NAME PARAMETER Data Setup t DSU Data Hold t DH FIGURE 5. EEPROM DATA ...

Page 12

ISL6590 Data Write Protocol 5 clocks 5 clocks CLK DATA Start Address: Address: DeviceID Register ISL6590 Data Read Protocol 5 clocks 5 clocks SCLK SDATA Start Address: DeviceID Address: Register 12 ISL6590 8 Clocks R/W Dead Ack Data Byte (to ...

Page 13

ASYNCHRONOUS ATX SERIAL INTERFACE ARX (ASI) Backside Serial Bus (BSB) The transfer of data on the BSB consists of a start bit bits, 5 memory address bits, a read/write bit, an address acknowledge bit, 8 data bits, a ...

Page 14

Address Cycle Address Cycle 10 clocks 10 clocks SCLK SCLK SDATA SDATA Start Start Configcall Configcall "0000000000" "0000000000" PWM1 PWM1 ("ID" register enable) ("ID" register enable) MHz Power IC Configuration Process First the master will initiate “config call” by sending ...

Page 15

Loop Compensation Any closed loop system must be designed to insure stability (prevent oscillation) and provide correct response to external events such as load transients. The output of a buck regulator has an inherent, low pass filter formed by the ...

Page 16

Adjusting The Digital PID FIGURE 16. DIGITAL PID COMPENSATOR Frequency response of the digital PID compensator is determined by the Kp, Ki, Kd factors. These factors are stored in nonvolatile memory and are loaded in the controller at power on ...

Page 17

Frequency (in KHz) FIGURE 20. PID COMPENSATOR FREQUENCY RESPONSE 60 40 Loop Phase 20 0 -20 -40 -60 -80 -100 -120 1 10 100 Frequency (in KHz) FIGURE 21. FREQUENCY ...

Page 18

FIGURE 23. PRIMARION POWERCODE LOADLINE AND ATR SETTINGS FIGURE 24. PRIMARION POWERCODE LOOP RESPONSE SETTINGS 18 ISL6590 FIGURE 25. PRIMARION POWERCODE MONITOR WINDOW FIGURE 26. PRIMARION POWERCODE DESIGN INPUTS FIGURE 27. PRIMARION POWERCODE DUTY CYCLE LIMIT SELECTION ...

Page 19

Register Description Tables ADDRESS RANGE VOLATILE MEMORY 0000 - 01FF General Control Registers 0000 Part Number (ASCII character #1) 0001 Part Number (ASCII character #2) 0002 Part Number (ASCII character #3) 0003 Part Number (ASCII character #4) 0004 Version Number ...

Page 20

ADDRESS RANGE 020A VID_IN_SOFT 020B Alive Found 020D Reserved 020E VCODE_IN 020F VCODE_OUT 0210 Enumeration Control 0211 Enumeration Done 0212 VID_IN (from VID pins) 0213 OUTEN (from OUTEN pin) 0214 PWRGD 0215 VID_OUT 0216 Voltage Error 0217 Average Peak Channel ...

Page 21

ADDRESS RANGE 0401 Reserved 0402 HFWND (High ATR Window) 0403 LFWND (Low ATR Window) 0404 VID (7 bit Voltage Identification) 0405 ILIM (Current Limit) 0406 TSD (Thermal Shutdown) 0407 Reserved 0408 TEST 0409 ENABLE1 (Block Enables LSB) 040A ENABLE2 (Block ...

Page 22

ADDRESS RANGE 0809 A/D ID 080A WCOMP ID 080B OUVP ID 080C MG Poll Priority 080D State Control 080E Reserved 080F Phases to be Used 0810 POR Wait 0811 Regulation Window 0812 Regulation Time 0813 Voltage Calibration Maximum 0814 Reserved ...

Page 23

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

Page 24

Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP D D1 INDEX 1 AREA TOP VIEW 0. SEATING SIDE VIEW ...

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