isl6551irec Intersil Corporation, isl6551irec Datasheet
isl6551irec
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isl6551irec Summary of contents
Page 1
... ISL6551IREC with companion Intersil ICs, Supervisor and Monitor ISL6550 and Half-bridge Driver HIP2100, is presented in Application Note AN1002. In addition, the ISL6551IREC can also be designed in push- pull converters using all of the features except the two upper drivers and adjustable resonant delay features. 1 ...
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... Ordering Information PART NUMBER ISL6551IREC ISL 6551IR ISL6551IR-TEC* ISL 6551IR *Please refer to TB347 for details on reel specifications. Pinout R_RESDLY 2 ISL6551IREC PART TEMP RANGE MARKING (° + +85 ISL6551IREC (28 LD QFN) TOP VIEW R_RA 2 ISENSE 3 PKILIM 4 BGREF 5 R_LEB ...
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... VDDP2, VDDP1 25 VDD 3 ISL6551IREC Reference ground. All control circuits are referenced to this pin. Set the oscillator frequency 1MHz. Adjust the clock dead time from 50ns to 1000ns. Program the resonant delay from 50ns to 500ns. Adjust the ramp for slope compensation (from 50mV to 250mV). ...
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... ADJUST 5 R_RA 2 CT CLOCK 3 GENERATOR RD ERROR AMP (SEE FIG. 4) EAO 14 13 EAI EANI CIRCUITS REFERENCED TO VSS 4 ISL6551IREC SHUTDOWN SHUTDOWN UVLO LATCH LATCH SHUTDOWN SHUTDOWN LEB PWM LOGIC CURRENT SHARE EXTERNAL SINGLE POINT CONNECTION REQUIRED SOFT SOFT- START START VDDP1 27 UPPER1 ...
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... Maximum Offset Error Voltage Input Common Mode Range Common Mode Rejection Ratio Power Supply Rejection Ratio Maximum Output Source Current 5 ISL6551IREC Thermal Information Thermal Resistance QFN Package (Notes 1, 2 Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C ...
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... Resonant Delay Leading Edge Blanking Adjust Range Leading Edge Blanking LATCHING SHUTDOWN (LATSD) Fault Threshold Fault_NOT Threshold Time to Set latch (Note 3) ON/OFF (ONOFF) Turn-off Threshold Turn-on Threshold 6 ISL6551IREC A SYMBOL TEST CONDITIONS Vsatlow Sinking 0.27mA F LVR IpkThr BGREF = 0.1µF, 399kΩ pull-up IpkDel Iss Vcss = 0 ...
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... Input Reference Threshold (Relative to Vref_in) Recovery (Relative to Vref_in) Threshold (Relative to Vref_in) Recovery (Relative to Vref_in) Transient Rejection (Note 3) NOTE: 3. Limits established by characterization and are not production tested. 7 ISL6551IREC A SYMBOL TEST CONDITIONS Vcs_offset SHARE = 30k SHARE = 30K, Rsource = 1k, OUTPUT REFERENCE = 1 to 5V, (See Figure 10 CS_COMP = 0.1µ ...
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... R_LEB pin with a resistor. Internal switches gate the analog input to the PWM comparator, implementing the blanking function that eliminates response degrading delays, which would be 8 ISL6551IREC caused if filtering of the current feedback was incorporated. The dead time (t3 and t5) is the delay to turn on the upper ...
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... C (LATCHING SHUTDOWN) The IC is latched off completely as the LATSD pin is pulled high, and the soft-start capacitor is reset. D (ON/OFF) The latch cannot be reset by the ON/OFF. 9 ISL6551IREC LATCH CANNOT BE RESET BY ON/OFF OVERCURRENT LATCHED OFF/ON E (LATCH RESET) The latch is reset by removing the VDD ...
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... I_CT VMAX CT CT I_CT 10 ISL6551IREC • This pin must also be decoupled with an 0.1µF low ESR ceramic capacitor. Clock Generator (CT, RD) • This free-running oscillator is set by two external components, as shown in Figure 2. A capacitor charged and discharged with two equal constant current sources and fed into a window comparator to set the clock frequency ...
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... EANI voltage is higher than the soft-start voltage. Thus, both the output voltage and current of the power supply can be controlled by the soft-start. 11 ISL6551IREC • The clamping voltage determines the cycle-by-cycle peak current limiting of the power supply. It should be set above the EANI and EAO voltages and can be programmed by an external resistor, as shown in Figure 5 using Equation 3 ...
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... ON/OFF (ON/OFF) • A high standard TTL input (safe also for VDD level) signals the controller to turn on. A low TTL input turns off the controller and terminates all drive signals including the SYNC outputs. The soft-start is reset. 12 ISL6551IREC (SEE FIG. 9) 400mV + SSL - ...
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... BLANKING TIME R_LEB FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS 13 ISL6551IREC Ramp Adjust (R_RA, ISENSE) • The ramp adjust block adds an offset component (200mV) and a slope adjust component to the ISENSE signal before processing it at the PWM Logic block, as shown in Figure 9 ...
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... The bandwidth of the current sharing loop should be much lower than that of the voltage loop to eliminate noise pick- up and interactions between the voltage regulation loop and the current loop. A 0.1µF capacitor is recommended 14 ISL6551IREC 30mV ADJ - + OTA FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT between CS_COMP and VSS pins to achieve a low current sharing loop bandwidth (100Hz to 500Hz) ...
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... Figure 13 shows the block diagram of a power supply system employing the ISL6551IREC full bridge controller. The ISL6551IREC not only is a full bridge PWM controller but also can be used as a push-pull PWM controller. Users can design a power supply by selecting appropriate blocks in the System Blocks Chart based on the power system requirements ...
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... V IN INPUT PRIMARY FILTER FETs PRIMARY FET CURRENT SENSE FIGURE 13. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551IREC CONTROLLER System Blocks Chart Input Filters FIGURE 13A. GENERAL FIGURE 13B. EMI GENERAL Input capacitors are required to absorb the power switch (FET) pulsating currents ...
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... Four MOSFETs are required for full bridge converters. The drain to source voltage rating of the MOSFETs is Vin. PUSH-PULL Only the two lower MOSFETs are required for push-pull converters. The two upper drivers are not used. The V the MOSFETs is 2xVin. 17 ISL6551IREC Feedback VOPOUT VOPOUT Q2 Q4 Q4_S ...
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... OUT P– S– FIGURE 18B. CONVENTIONAL FULL BRIDGE 18 ISL6551IREC SCHOTTKY FIGURE 18C. PUSH-PULL AND CURRENT DOUBLER FULL BRIDGE AND CURRENT DOUBLER No center tap is required. The secondary winding carries half of the load, i.e., only half of the load is reflected to the primary. CONVENTIONAL FULL BRIDGE Center tap is required on the secondary side, and no center tap is required on the primary side ...
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... CS_COMP SYNC2 OFF CSS 11 18 EANI DCOK 12 17 EAI LSTSD 13 16 EAO SHARE 15 14 FIGURE 21. ISL6551IREC CONTROLLER MIC4421BM MIC4421BM SYNC1 IN OUT IN SYNP /LOWER2 GND FIGURE 22A. INVERTING DRIVERS MIC4422BM MIC4422BM IN OUT SYNC2 IN OUT SYNP GND GND FIGURE 22B. NON-INVERTING DRIVERS ...
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... Upper drivers are not used. No external drivers are required. Secondary control. Operate at the switching frequency. Push-Pull High Current Drivers Upper drivers are not used. External high current drivers are required and less power is dissipated in the ISL6551IREC controller. Secondary control. Operate at the switching frequency. Push-Pull Primary Control Upper drivers are not used ...
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... FULL BRIDGE DRIVERS FULL BRIDGE HIGH CURRENT DRIVERS External high current drivers are required and less power is dissipated in the ISL6551IREC controller. Secondary control. Operate at the switching frequency. FULL BRIDGE MEDIUM CURRENT DRIVERS No external drivers are required. Secondary control. Operate at the switching frequency. ...
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Simplified Typical Application Schematics SB+12V UPPER1 UPPER2 LOWER1 LOWER2 SA+12V + OUT - PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 LED SHARE BUS 200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS) SB+48V VDD LO HB VSS ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 ISL6551IREC L28.6x6 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) ...