S25FL064K Meet Spansion Inc., S25FL064K Datasheet
S25FL064K
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S25FL064K Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL064K_00 Notice On Data Sheet Designations Revision 02 Issue Date September 16, 2010 S25FL064K Cover Sheet for definitions. ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL064K S25FL064K_00_02 September 16, 2010 ...
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... SO package (300 mils) – 8-pin SO package (208 mils) Publication Number S25FL064K_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications ...
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... Pages can be erased in groups sector erase), groups of 128 (32 KB block erase), groups of 256 (64 KB block erase) or the entire chip (chip erase). The S25FL064K has 2048 erasable sectors and 128 erasable blocks respectively. The small 4 KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... Erase Security Registers (44h 7.34 Program Security Registers (42h 7.35 Read Security Registers (48h Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 Power-up Timing and Write Inhibit Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.5 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 September 16, 2010 S25FL064K_00_02 S25FL064K 5 ...
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... Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1 SO3016 — 16-pin Plastic Small Outline Package (300-mils Body Width 9.2 SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width 10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL064K S25FL064K_00_02 September 16, 2010 ...
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... Program Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 7.39 Read Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 8.1 Power-up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 8.2 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 8.3 Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 8.4 Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 8.5 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 September 16, 2010 S25FL064K_00_02 S25FL064K 7 ...
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... Tables Table 3.1 8-pin SOIC 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 3.2 16-pin SOIC 300-MIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 4.1 S25FL064K Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 6.1 Status Register Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 6.2 Status Register Memory Protection (CMP = .17 Table 6.3 Status Register Memory Protection (CMP = .18 Table 7.1 Manufacturer Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 7.2 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 7.3 Instruction Set (Erase, Program Instructions (1 .19 Table 7 ...
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... WP# (IO2) HOLD# (IO3) CLK CLK CS# SI (IO0) SO (IO1) September 16, 2010 S25FL064K_00_02 SFDP Register SFDP Register 0000FFh 0000FFh xxFFFFh xxFFFFh Sector 15 (4 KB) • xxF0FFh xxF0FFh xxEFFFh xxEFFFh Sector 14 (4 KB) • ...
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... Write Protect Input (Data Input Output 2) GND Ground SI (IO0) I/O Data Input (Data Input Output 0) CLK I Serial Clock Input HOLD# (IO3) I/O Hold Input (Data Input Output 3) VCC Power Supply S25FL064K 8 VCC 7 HOLD# (IO3) CLK (IO0) SCK SI/IO0 N/C N/C N/C N/C GND 9 W#/ACC/IO2 Function (1) (2) (1) (2) S25FL064K_00_02 September 16, 2010 ...
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... Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions September 16, 2010 S25FL064K_00_02 Table 3.2 16-pin SOIC 300-MIL Pin Name I/O HOLD# (IO3) ...
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... Device Family S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 4.1 S25FL064K Valid Combinations S25FL064K Valid Combinations Package & Speed Option Temperature 0S MFI S25FL064K Packing Type 0 = Tray 1 ...
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... Dual SPI Instructions The S25FL064K supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP) ...
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... Lock Down write protection until next power-up One Time Program (OTP) write protection Upon power- power-down, the S25FL064K will maintain a reset condition while V threshold value of VWI, (see operations are disabled and no instructions are recognized. During power-up and after the V ...
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... The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. September 16, 2010 S25FL064K_00_02 61) ...
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... Status Register Protect 0 (non-volatile) Sector Protect (non-volatile) Top/Bottom Protect (non-volatile) Block Protect Bits (non-volatile) Write Enable Latch Erase/Write In Progress S25FL064K Description ( BP2 BP2 BP1 BP1 BP0 BP0 WEL BUSY WEL BUSY S25FL064K_00_02 September 16, 2010 ...
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... Security Register Lock Bits (non-volatile OTP) Reserved Quad Enable (non-volatile) Status Register Protect 1 (non-volatile) ( Table 6.2 Status Register Memory Protection (CMP = 0) (1) S25FL064K (64 MBit) Memory Protection BP1 BP0 Protected Block(s) Protected Addresses 0 0 None 0 1 126 and 127 7E0000h – 7FFFFFh ...
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... L = Lower Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. 7. Instructions The instruction set of the S25FL064K consists of thirty five basic instructions that are fully controlled through the SPI bus (see Table 7.3 Select (CS#) ...
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... Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……) 4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See on page 37 for more information. September 16, 2010 S25FL064K_00_02 Table 7.1 Manufacturer Identification (MF7-MF0) Table 7 ...
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... IO2 = IO3 = S25FL064K BYTE 4 BYTE 5 BYTE 6 A7–A0 (D7–D0) A7–A0 dummy (D7–D0) A7–A0 dummy (D7–D0, …) A7–A0 dummy (D7–D0, …) (D7–D0, …) (1) (D7–D0, …) (3) (5) (D7–D0, …) (3) (6) (3) S25FL064K_00_02 September 16, 2010 (1) (3) ...
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... CS# low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge of CLK, and then driving CS# high. CS# Mode 3 CLK Mode September 16, 2010 S25FL064K_00_02 Table 7.5 Instruction Set (ID, Security Instructions) BYTE 1 BYTE 2 BYTE 3 (CODE) ...
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... Write Enable Latch (WEL) bit Instruction (50h) High Impedance Figure 7.3 Write Disable Instruction Sequence Diagram Instruction (04h) High Impedance S25FL064K can also be written 6 7 Mode 3 Mode 0 7 Mode 3 Mode 0 S25FL064K_00_02 September 16, 2010 ...
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... Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. September 16, 2010 S25FL064K_00_02 Figure 6 ...
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... Instruction (03h) 24-Bit Address High Impedance S25FL064K (see Section 8.6, AC SHSL2 (see Data Out S25FL064K_00_02 September 16, 2010 Mode 3 Mode 0 See AC Data Out 2 7 ...
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... Mode 3 CLK Mode CS CLK Dummy Byte MSB September 16, 2010 S25FL064K_00_02 (see See AC Electrical Characteristics on page R Figure 7.7 Fast Read Instruction Sequence Diagram 24-Bit Address ...
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... The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL064K at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution ...
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... IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the S25FL064K at four times the rate of standard SPI devices. ...
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... Byte 2 Byte 3 Byte 4 S25FL064K Figure 7.10. The upper nibble of the Figure 7.11. This reduces 37.). M7-0 A15-8 A7 S25FL064K_00_02 September 16, 2010 ...
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... Figure 7.11 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 0 CLK Mode 0 IO0 6 IO1 7 CS CLK IO0 IO1 Byte 1 September 16, 2010 S25FL064K_00_02 ...
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... The upper nibble of the (M7-4) Figure 7.13, Fast Read 31. This reduces the instruction 37 Switches from Input to Output Byte 2 Dummy Dummy Byte 1 M7-0 S25FL064K_00_02 September 16, 2010 ...
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... The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See Section 7.14, Set Burst with Wrap (77h) on page September 16, 2010 S25FL064K_00_02 ...
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... The upper nibble of the Figure 7.15. This reduces 37 Switches from Input to Output Byte 2 Dummy Byte 1 Byte 3 M7-0 S25FL064K_00_02 September 16, 2010 ...
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... The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See Section 7.14, Set Burst with Wrap (77h) on page September 16, 2010 S25FL064K_00_02 ...
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... This reduces the 37 Switches from Input to Output Byte 2 Dummy Byte 1 Byte 3 M7-0 S25FL064K_00_02 September 16, 2010 ...
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... Figure 7.17 Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 CLK Mode 0 IO0 IO1 IO2 IO3 September 16, 2010 S25FL064K_00_02 ...
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... The default value of W4 upon power the case of a system Reset while recommended that the controller issues a Set Burst with Wrap instruction to reset prior to any normal Read instructions since S25FL064K does not have a hardware Reset Pin. CS# ...
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... IO2 IO3 Since S25FL064K does not have a hardware Reset pin the controller resets while S25FL064K is set to Continuous Mode Read, the S25FL064K will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... Instruction (02h) 24-Bit Address S25FL064K Figure 7.20, Page Program (See AC Electrical Data Byte S25FL064K_00_02 September 16, 2010 0 ...
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... CLK Byte 5 IO0 IO1 IO2 IO3 MSB September 16, 2010 S25FL064K_00_02 Figure 7.21 Quad Page Program Instruction Sequence Diagram Instruction (32h) 24-Bit Address ...
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... See AC Electrical Characteristics on page 61. SE Figure 7.22 Sector Erase Instruction Sequence Diagram Mode 3 Mode 0 Instruction (20h High Impedance = MSB S25FL064K See Block Diagram on page 9. The Sector While the Sector 17 Mode 3 Mode 0 24-Bit Address S25FL064K_00_02 September 16, 2010 ...
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... Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 6.2, Status Register Memory Protection (CMP = 0) on page CS# CLK SIO SO September 16, 2010 S25FL064K_00_02 Figure 7.23. (See AC Electrical Characteristics on page BE1 Figure 7 ...
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... See AC Electrical Characteristics on page BE Figure 7. Block Erase Instruction Sequence Diagram Instruction (D8h) High Impedance S25FL064K See Block Diagram on page 9. The Block 61.). While the Block 17 Mode 3 Mode 0 24-Bit Address S25FL064K_00_02 September 16, 2010 ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see (CMP = 0) on page 17). CS# CLK September 16, 2010 S25FL064K_00_02 (See AC Electrical Characteristics on page CE Figure 7.25 Chip Erase Instruction Sequence Diagram ...
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... AC Electrical Characteristics on page SUS ” following the preceding Resume instruction “7Ah”. SUS Figure 7.26 Erase/Program Suspend Instruction Sequence Instruction (75h) High Impedance S25FL064K Figure 7.26, Erase/Program Suspend 61.) is required to t SUS Mode 3 Mode 0 Accept Read or Program Instruction S25FL064K_00_02 September 16, 2010 ...
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... It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “t CS# 0 Mode 3 CLK Mode 0 SI September 16, 2010 S25FL064K_00_02 ” following a previous Resume instruction. SUS Figure 7.27 Erase/Program Resume Instruction Sequence 1 2 ...
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... The instruction is initiated by driving the CS# pin low and shifting the Figure 7.28. (See AC Electrical Characteristics on page Figure 7.28 Deep Power-down Instruction Sequence Diagram Instruction (B9h) S25FL064K Section 8.4, DC 61.). While in the power-down state only the t DP Mode 3 Mode 0 Standard Current Deep Power-down Current S25FL064K_00_02 September 16, 2010 ...
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... CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for the S25FL064K is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving CS# high. ...
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... After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in ID values for the S25FL064K is listed in initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
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... The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction. September 16, 2010 S25FL064K_00_02 Figure 7.32. The Device ID values for the S25FL064K is listed in 19. If the 24-bit address is initially set to 000001h the Device ID will Figure 7.32 Read Manufacturer / Device ID Dual I/O Diagram S25FL064K 49 ...
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... Address bits four bits per clock. After which, the Manufacturer ID and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in ID values for the S25FL064K is listed in initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each S25FL064K device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS# pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the S25FL064K provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial flash memories that was adopted in 2003. The instruction is initiated by driving the CS# pin low and shifting the instruction code “ ...
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... Read SFDP Register (5Ah) The S25FL064K features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified but more may be added in the future ...
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... Serial Flash Basics Revision 1.0 4 Dwords (2) PID(0) Table Address = 000080h EFh Serial Flash Properties Revision 1.0 00h = Unimplemented PID(1) Table Address = 000090h 64 Mega Bits =03FFFFFFh Fast Read Quad I/O Setting Fast Read Quad Output Setting Fast Read Dual Output Setting Fast Read Dual I/O Setting S25FL064K_00_02 September 16, 2010 ...
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... 7.33 Erase Security Registers (44h) The S25FL064K offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Byte Address Byte Address Figure 7.38. The Security Register Lock Bits and Page Program Data Byte Data Byte 256 S25FL064K_00_02 September 16, 2010 0 Mode 3 Mode 0 ...
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... Security Register #2 Security Register #3 CS# Mode 3 CLK Mode CS# 32 CLK MSB September 16, 2010 S25FL064K_00_02 61). A23-16 A15-12 00h 00h 00h Figure 7.39 Read Security Registers Instruction Sequence 0 1 ...
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... Electrical Characteristics Specification for S25FL064K is Advance Information. See of this document. 8.1 Absolute Maximum Ratings Parameters Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. ...
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... Output High Voltage Notes: 1. Tested on sample basis and specified through design and characterization data 25° Checker Board Pattern. September 16, 2010 S25FL064K_00_02 Figure 8.1 Power-up Timing and Voltage Levels Program, Erase, and Write instructions are ignored ...
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... Symbol OUT Figure 8.2 AC Measurement I/O Waveform Input and Output Input Levels Timing Reference Levels 0.8 VCC 0.2 VCC S25FL064K Spec Unit Min Max 0.5 VCC S25FL064K_00_02 September 16, 2010 ...
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... Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set For multiple bytes after first byte within a page, t bytes programmed. 5. Max Value t with <50K cycles is 200 ms and >50K & <100K cycles is 400 ms. SE September 16, 2010 S25FL064K_00_02 Symbol F R ...
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... Figure 8.3 Serial Output Timing tCLQV tCLL tQLQH tQHQL Figure 8.4 Serial Input Timing t SLCH t DVCH t CHDX MSB IN (High Impedance) Figure 8.5 Hold Timing tHLCH tCHHL tCHHH tHLQZ S25FL064K tCLH tSHQZ LSB Out t SHSL t t CHSH SHCH t t CLCH CHCL LSB IN tHHCH tHHQX S25FL064K_00_02 September 16, 2010 ...
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... September 16, 2010 S25FL064K_00_02 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS ...
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... THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED FROM THE SEATING PLANE. S25FL064K WITH PLATING (b) BASE 7 METAL SECTION A 0.07 R MIN. GAUGE PLANE A SEATING PLANE DETAIL B 3432 \ 16-038.03 \ 10.28.04 S25FL064K_00_02 September 16, 2010 ...
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... Program Security Registers Corrected table Read Security Registers Corrected table AC Electrical Characteristics Added Alternate description for Clock High, Low Time except Read Data (03h) Serial Output Timing Update timing diagram September 16, 2010 S25FL064K_00_02 Description S25FL064K 65 ...
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... Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion logo, MirrorBit , MirrorBit S25FL064K ® Eclipse™, ORNAND™, EcoRAM™ S25FL064K_00_02 September 16, 2010 ...