S25FL128K Meet Spansion Inc., S25FL128K Datasheet
S25FL128K
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S25FL128K Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL128K_00 Notice On Data Sheet Designations Revision 02 S25FL128K Cover Sheet for definitions. Issue Date April 1, 2011 ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL128K S25FL128K_00_02 April 1, 2011 ...
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... Industry Standard Pinouts – 16-pin SO package (300 mils) Publication Number S25FL128K_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications ...
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... Pages can be erased in groups sector erase), groups of 128 (32 kB block erase), groups of 256 (64 kB block erase) or the entire chip (chip erase). The S25FL128K has 4096 erasable sectors and 256 erasable blocks respectively. The small 4 kB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.6 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.7 Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.8 Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.9 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1 SO3016 — 16-pin Plastic Small Outline Package (300-mils Body Width Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 April 1, 2011 S25FL128K_00_02 S25FL128K 5 ...
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... Figure 6.41 Read Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 7.1 Power-up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 7.2 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 7.3 Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 7.4 Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 7.5 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL128K S25FL128K_00_02 April 1, 2011 ...
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... Tables Table 3.1 16-pin SOIC 300-MIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 4.1 S25FL128K Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 6.1 Status Register Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 6.2 Status Register Memory Protection (CMP = .15 Table 6.3 Status Register Memory Protection (CMP = .16 Table 6.4 Manufacturer Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 6.5 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 6.6 Instruction Set (Erase, Program Instructions (1 .17 Table 6 ...
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... Block 0 (64 KB) • 000000h 000000h 0000FFh 0000FFh Beginning Beginning Ending Ending Page Address Page Address Page Address Page Address Column Decode Column Decode And 256-Byte Page Buffer And 256-Byte Page Buffer S25FL128K_00_02 April 1, 2011 ...
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... Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions. 2. IO0 – IO3 are used for Quad SPI instructions. April 1, 2011 S25FL128K_00_02 Figure 2.1 16-pin Plastic Small Outline Package (SO HOLD#/IO3 ...
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... Device Family S25FL Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory Table 4.1 S25FL128K Valid Combinations S25FL128K Valid Combinations Package & Speed Option Temperature 0X MFI S25FL128K Packing Type 0 = Tray 1 ...
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... Dual SPI Instructions The S25FL128K supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP) ...
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... Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the S25FL128K provides several means to protect the data from inadvertent writes. 5.2.1 Write Protect Features ...
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... The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. April 1, 2011 S25FL128K_00_02 54) ...
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... Status Register Protect 0 (non-volatile) Sector Protect (non-volatile) Top/Bottom Protect (non-volatile) Block Protect Bits (non-volatile) Write Enable Latch Erase/Write In Progress S25FL128K Description ( BP2 BP2 BP1 BP1 BP0 BP0 WEL BUSY WEL BUSY S25FL128K_00_02 April 1, 2011 ...
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... Security Register Lock Bits (non-volatile OTP) Reserved Quad Enable (non-volatile) Status Register Protect 1 ( (non-volatile) Table 6.2 Status Register Memory Protection (CMP = 0) (1) S25FL128K (128 Mbit) Memory Protection BP1 BP0 Protected Block(s) Protected Addresses 0 0 None 0 1 252 thru 255 FC0000h – FFFFFFh ...
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... If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. 6.2 Instructions The instruction set of the S25FL128K consists of thirty five basic instructions that are fully controlled through the SPI bus (see Table 6.6 Select (CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……) 4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See on page 33 for more information. April 1, 2011 S25FL128K_00_02 Table 6.4 Manufacturer Identification (MF7-MF0) Table 6 ...
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... IO2 = IO3 = S25FL128K Byte 4 Byte 5 Byte 6 A7–A0 (D7–D0) A7–A0 dummy (D7–D0) A7–A0 dummy (D7–D0, …) A7–A0 dummy (D7–D0, …) (D7–D0, …) (1) (D7–D0, …) (3) (5) (D7–D0, …) (3) (6) (3) S25FL128K_00_02 April 1, 2011 (1) (3) ...
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... Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. April 1, 2011 S25FL128K_00_02 Table 6 ...
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... High Impedance and Figure 6.2 and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE, Section 6.1, Status Register on page S25FL128K 6.4) will not set the Write Enable Latch (WEL) bit Mode 3 Mode Mode 3 Mode 0 Figure 6.6. The Status Register bits are 13). S25FL128K_00_02 April 1, 2011 ...
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... Register bits will be refreshed to the new values within the time period of t Electrical Characteristics on page Refer to Section 6.1, Status Register on page 13 for all status Register bits are 0. April 1, 2011 S25FL128K_00_02 Figure 6.6 Read Status Register Instruction Sequence Diagram 2 ...
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... Instruction (03h) 24-Bit Address High Impedance S25FL128K (see Data Out S25FL128K_00_02 April 1, 2011 Mode 3 Mode 0 See AC Data Out 2 7 ...
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... Mode 3 CLK Mode CS CLK Dummy Byte MSB April 1, 2011 S25FL128K_00_02 (see See AC Electrical Characteristics on page R Figure 6.9 Fast Read Instruction Sequence Diagram 24-Bit Address ...
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... The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL128K at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution ...
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... IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the S25FL128K at four times the rate of standard SPI devices. ...
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... Byte 2 Byte 3 Byte 4 S25FL128K Figure 6.12. The upper nibble of the Figure 6.13. This reduces 33.). A15-8 A7-0 M7 S25FL128K_00_02 April 1, 2011 ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (see Section 6.2.16, Continuous Read Mode Reset (FFh or FFFFh) on page April 1, 2011 S25FL128K_00_02 ...
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... Byte 2 Dummy Dummy Byte 1 M7 Switches from Input to Output Dummy Byte 1 Byte 2 32. S25FL128K_00_02 April 1, 2011 ...
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... Section 6.2.16, Continuous Read Mode Reset (FFh or FFFFh) on page Figure 6.16 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) CS# Mode Mode 0 CLK Instruction (E7h) IO0 IO1 IO2 IO3 April 1, 2011 S25FL128K_00_02 ...
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... A15-8 A7-0 M7-0 S25FL128K Switches from Input to Output Byte 2 Byte 1 Byte 3 32. Figure 6.18, Octal 10) on page 31. The upper Figure 6.19, Octal Word 31. This reduces the 33). S25FL128K_00_02 April 1, 2011 ...
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... IO0 IO1 IO2 IO3 Figure 6.19 Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 CLK Mode 0 IO0 IO1 IO2 IO3 April 1, 2011 S25FL128K_00_02 Instruction (E3h) ...
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... The default value of W4 upon power the case of a system Reset while recommended that the controller issues a Set Burst with Wrap instruction to reset prior to any normal Read instructions since S25FL128K does not have a hardware Reset Pin. CS# ...
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... IO2 IO3 Since S25FL128K does not have a hardware Reset pin the controller resets while S25FL128K is set to Continuous Mode Read, the S25FL128K will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... Instruction (02h) 24-Bit Address S25FL128K Figure 6.22, Page Program . See AC Electrical Data Byte S25FL128K_00_02 April 1, 2011 0 ...
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... CLK Byte 5 IO0 IO1 IO2 IO3 MSB April 1, 2011 S25FL128K_00_02 Figure 6.23 Quad Page Program Instruction Sequence Diagram Instruction (32h) 24-Bit Address ...
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... Instruction (20h High Impedance = MSB Figure 6.25. (See AC Electrical Characteristics on page BE1 S25FL128K See Block Diagram on page 8. The Sector While the Sector 15 Mode 3 Mode 0 24-Bit Address See Block Diagram on page 8. The Block 54.). While the Block 15. S25FL128K_00_02 April 1, 2011 ...
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... The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence April 1, 2011 S25FL128K_00_02 Figure 6 ...
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... High Impedance SO 39. ” (See AC Electrical Characteristics on page SUS ” following the preceding Resume instruction “7Ah”. SUS S25FL128K While the Chip Erase cycle is in Table 6.2, Status Register Memory Protection Mode 3 Mode 0 Figure 6.28, Erase/Program Suspend 54.) is required to S25FL128K_00_02 April 1, 2011 ...
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... It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “t CS# 0 Mode 3 CLK Mode 0 SI April 1, 2011 S25FL128K_00_02 Figure 6.28 Erase/Program Suspend Instruction Sequence ...
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... CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for the S25FL128K is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving CS# high. ...
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... CLK SI SO Figure 6.32 Release from Deep Power-down / Device ID Instruction Sequence Diagram CS# Mode CLK Mode 0 Instruction (ABh MSB April 1, 2011 S25FL128K_00_02 Instruction (ABh) High Impedance Deep Power-down Current ...
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... After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in ID values for the S25FL128K is listed in initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
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... The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction. April 1, 2011 S25FL128K_00_02 Figure 6.34. The Device ID values for the S25FL128K is listed in 17. If the 24-bit address is initially set to 000001h the Device ID will Figure 6.34 Read Manufacturer / Device ID Dual I/O Diagram S25FL128K 43 ...
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... Address bits four bits per clock. After which, the Manufacturer ID and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in ID values for the S25FL128K is listed in initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each S25FL128K device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS# pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the S25FL128K provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial flash memories that was adopted in 2003. The instruction is initiated by driving the CS# pin low and shifting the instruction code “ ...
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... Read SFDP Register (5Ah) The S25FL128K features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified but more may be added in the future ...
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... Dwords (2) PID(0) Table Address = 000080h EFh Serial Flash Properties Revision 1.0 00h = Unimplemented PID(1) Table Address = 000090h 128 Mega Bits =07FFFFFFh Fast Read Quad I/O Setting Fast Read Quad Output Setting Fast Read Dual Output Setting Fast Read Dual I/O Setting S25FL128K_00_02 April 1, 2011 ...
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... 6.2.33 Erase Security Registers (44h) The S25FL128K offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Byte Address Byte Address Figure 6.40. The Security Register Lock Bits and Page Program Data Byte Data Byte 256 S25FL128K_00_02 April 1, 2011 0 Mode 3 Mode 0 ...
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... Security Register #2 Security Register #3 CS# Mode 3 CLK Mode CS# 32 CLK MSB April 1, 2011 S25FL128K_00_02 54). A23-16 A15-12 00h 00h 00h Figure 6.41 Read Security Registers Instruction Sequence 0 1 ...
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... Electrical Characteristics Specification for S25FL128K is Advance Information. See of this document. 7.1 Absolute Maximum Ratings Parameters Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. ...
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... Output High Voltage Notes: 1. Tested on sample basis and specified through design and characterization data 25° Checker Board Pattern. April 1, 2011 S25FL128K_00_02 Figure 7.1 Power-up Timing and Voltage Levels Program, Erase, and Write instructions are ignored ...
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... CC CC 0.5 VCC Spec Alt Min Typ Max f D. D.C. 104 C D. 0.1 0 CSS DSU CSH 50 t CSH DIS 8.5 / 7.5 V2 S25FL128K_00_02 April 1, 2011 Unit MHz MHz MHz V/ns V/ ...
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... SE 7.7 Serial Output Timing CS# CLK tCLQV tCLQX tCLQX SO/SIO* *SIO is an output only for the fast read dual output instructions (3Bh) April 1, 2011 S25FL128K_00_02 Symbol t CLQX t HLCH t CHHH t ...
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... Figure 7.4 Serial Input Timing t SLCH t DVCH t CHDX MSB IN (High Impedance) Figure 7.5 Hold Timing t HLCH t CHHL t CHHH t HLQZ S25FL128K t SHSL t t CHSH SHCH t t CLCH CHCL LSB IN t HHCH t HHQX S25FL128K_00_02 April 1, 2011 ...
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... April 1, 2011 S25FL128K_00_02 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS ...
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... Revision History Section Revision 01 (July 22, 2010) Initial release Revision 02 (April 1, 2011) Global Changed data sheet designation from Advance Information to Preliminary Description S25FL128K S25FL128K_00_02 April 1, 2011 ...
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... EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. April 1, 2011 S25FL128K_00_02 ® ...