S25FL129P Meet Spansion Inc., S25FL129P Datasheet
S25FL129P
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S25FL129P Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL129P_00 Notice On Data Sheet Designations Revision 04 Issue Date November 2, 2009 S25FL129P Cover Sheet for definitions. ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL129P S25FL129P_00_04 November 2, 2009 ...
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... RES command one-byte electronic signature for backward compatibility Publication Number S25FL129P_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications ...
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... General Description The S25FL129P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device is offered in two configurations: 256 uniform 64 KB sectors with the two (Top or Bottom sectors further split up into thirty-two 4 KB sub sectors uniform 256 KB sectors. The S25FL129P device is backward compatible with the S25FL128P (uniform 256 KB sector) device ...
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... OTP Program (OTPP 9.23 Read OTP Data Bytes (OTPR 10. OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 Programming OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 Reading OTP Data 10.3 Locking OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 November 2, 2009 S25FL129P_00_04 S25FL129P 5 ...
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... WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.3 FAB024 — 24-ball Ball Grid Array ( mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 19.4 FAC024 — 24-ball Ball Grid Array ( mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL129P S25FL129P_00_04 November 2, 2009 ...
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... AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 18.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 18.2 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 18.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 18.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = November 2, 2009 S25FL129P_00_04 S25FL129P 7 ...
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... Tables Table 5.1 S25FL129P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 7.1 Configuration Register Table (Uniform 64 KB sector .16 Table 7.2 Configuration Register Table (Uniform 256 KB sector .16 Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array .17 Table 7.4 TBPROT = 1 (Starts Protection from BOTTOM of Array .17 Table 8.1 S25FL129P Sector Address Table (Uniform 256 KB sector .19 Table 8 ...
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... Block Diagram 2. Connection Diagrams Note DNC = Do Not Connect (Reserved for future use) November 2, 2009 S25FL129P_00_04 SRAM Array - L Logic RD IO Figure 2.1 16-pin Plastic Small Outline Package (SO HOLD#/IO3 2 15 VCC 3 14 ...
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... SCK GND CS# NC W#/ACC/IO2 SO/IO1 SI/IO0 HOLD#/IO3 S25FL129P 8 VCC 7 HOLD#/IO3 6 SCK SI/IO0 VCC VCC S25FL129P_00_04 November 2, 2009 ...
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... Input CC GND Input 4. Logic Symbol November 2, 2009 S25FL129P_00_04 Description Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes. ...
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... B = Speed 0X = Device Technology P = Density 129 = Device Family S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL129P Valid Combinations Table S25FL129P Valid Combinations Package & Speed Option Temperature MFI, NFI MFV , NFV 0X BHI BHV S25FL129P (Note 1) Tray Tube 13” ...
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... The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL Mode 0 0 Mode 3 1 November 2, 2009 S25FL129P_00_04 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK ...
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... Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL129P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure. ...
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... TBPARM November 2, 2009 S25FL129P_00_04 Table 9.8, S25FL129P Status Register on page TBPROT 0 1 Not recommended (Parameters & BP Protection are both Bottom) 0 Not recommended (parameters & BP Protection are both Top) 1 S25FL129P 39): ...
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... Bottom Array (low address) (Default Quad I Dual or Serial I/O (Default Enabled 0 = Disabled (Default) Description Not Used Not Used 1 = Bottom Array (low address Top Array (high address) (Default) Do Not Use 1 = Volatile 0 = Non-volatile (Default) Do not Use 1 = Quad I Dual or Serial I/O (Default Enabled 0 = Disabled (Default) S25FL129P_00_04 November 2, 2009 ...
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... FFFFFFh November 2, 2009 S25FL129P_00_04 Memory Array Protected Sectors Uniform Uniform Unprotected 64 KB 256 KB Address Range 0 0 000000h - FFFFFFh SA255:SA0 SA63:SA0 (4) SA255:SA252 (1) SA63 ...
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... Note: The ACC function is disabled during Quad I/O Mode 7.1. Figure 7.1 Hold Mode Operation Hold Condition (standard use) S25FL129P Figure 7.1, standard use). If the Hold Condition (non-standard use) on this pin, the S25FL129P_00_04 November 2, 2009 ...
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... The data is erased (bits are changed from sub-sector, sector- or device-wide basis using the P4E/P8E (applicable only for the uniform 64 KB sector device commands. The complete set of sectors comprises the memory array of the Flash device. Table 8.1 S25FL129P Sector Address Table (Uniform 256 KB sector) Sector 63 62 ...
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... Table 8.2 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=0) (Sheet Address Range Sector Start Address SA108 6C0000h SA107 6B0000h SA106 6A0000h SA105 690000h SA104 680000h SA103 670000h SA102 660000h SA101 650000h SA100 640000h SA99 630000h SA98 620000h SA97 610000h SA96 ...
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... Table 8.2 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=0) (Sheet Address Range Sector Start Address SA255 FF0000h SA254 FE0000h SA253 FD0000h SA252 FC0000h SA251 FB0000h SA250 FA0000h SA249 F90000h SA248 F80000h SA247 F70000h SA246 F60000h SA245 F50000h SA244 ...
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... Table 8.3 S25FL129P Sector Address Table (Uniform 64KB sector, TBPARM=1) (Sheet Address Range Sector Start Address SS31 FFF000h SS30 FFE000h SS29 FFD000h SS28 FFC000h SS27 FFB000h SS26 FFA000h SS25 FF9000h SS24 FF8000h SS23 FF7000h SS22 FF6000h SS21 FF5000h SS20 FF4000h SS19 ...
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... Table 8.3 S25FL129P Sector Address Table (Uniform 64KB sector, TBPARM=1) (Sheet Address Range Sector Start Address SA143 8F0000h SA142 8E0000h SA141 8D0000h SA140 8C0000h SA139 8B0000h SA138 8A0000h SA137 890000h SA136 880000h SA135 870000h SA134 860000h SA133 850000h SA132 ...
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... The device ignores any attempt to access the memory array during a Write Registers, program, or erase operation, and continues the operation uninterrupted. The instruction set is listed Table 9.1 lists the complete set of commands. Table 9.1. S25FL129P S25FL129P_00_04 November 2, 2009 ...
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... OTPP (42h) 0100 0010 OTP OTPR (4Bh) 0100 1011 Note 1. For uniform 64 KB sector device only. November 2, 2009 S25FL129P_00_04 Table 9.1 Instruction Set Description Read Data bytes Read Data bytes at Fast Speed Dual Output Read ...
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... Figure 9.1 Read Data Bytes (READ) Command Sequence Command 24 Bit Address MSB S25FL129P ) presented Data Out 1 Data Out MSB S25FL129P_00_04 November 2, 2009 , R ...
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... Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS# Mode SCK Mode 0 SI Hi-Z SO November 2, 2009 S25FL129P_00_04 the falling edge of SCK. Figure 9 ...
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... Bit Instruction Address S25FL129P and Table 9.1 on page 25. The first Dummy Byte SI Switches from Input to Output Byte 1 Byte 2 S25FL129P_00_04 November 2, 2009 *MSB ...
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... CS SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 November 2, 2009 S25FL129P_00_04 Figure 9.4 Figure 9.4 Quad Output Read Instruction Sequence Bit ...
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... S25FL129P Figure 9.5 and Table 9.1 Figure 9.5). This added feature IO0 & IO1 Switches from Input to Output Mode Bits Byte 1 Byte 2 S25FL129P_00_04 November 2, 2009 *MSB ...
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... Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence CS# SCK 22 SI/IO0 SO/IO1 23 November 2, 2009 S25FL129P_00_04 Bit Address ...
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... Mode Bits S25FL129P Figure 9.7 and Table 9.1 on page Figure 9.7). This added feature the IO’s Switches from Input to Output DUMMY DUMMY Byte 1 Byte 2 S25FL129P_00_04 November 2, 2009 25. *MSB ...
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... Driving CS# high at any time during data output (for example, while reading the extended CFI bytes), also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. November 2, 2009 S25FL129P_00_04 ...
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... Address for Alternate OEM Extended Table (00h = none exists) 00h S25FL129P 652 653 654 655 Extended Device Information 644 645 646 1 647 Extended Device Identification Byte 2 Byte 3 Byte 4 18h 4Dh 00h 18h 4Dh 01h Description S25FL129P_00_04 November 2, 2009 ...
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... November 2, 2009 S25FL129P_00_04 Table 9.4 Product Group CFI System Interface String Data 27h V Min. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) CC 36h V Max. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) ...
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... Not Supported, (D7-D4: Volt, D3-D0: 100 mV) W# Protection 07h 07 = Uniform Device with Top or Bottom Write Protect (user select) Program Suspend 00h 00 = Not Supported Supported and time-outs of the product. Please consult the Ordering Information CC AC Characteristics on page 60 S25FL129P Description for typical timeout S25FL129P_00_04 November 2, 2009 ...
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... 9.8 Read-ID (READ_ID) The READ_ID instruction provides the S25FL129P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “ ...
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... Figure 9.11 Write Enable (WREN) Command Sequence CS Mode 3 SCK Mode 0 Command SI Hi-Z SO Figure 9.12) resets the Write Enable Latch (WEL) bit which Figure 9.12 Write Disable (WRDI) Command Sequence CS Mode 3 SCK Mode 0 Command SI Hi-Z SO S25FL129P S25FL129P_00_04 November 2, 2009 ...
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... BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page Program (PP), November 2, 2009 S25FL129P_00_04 Table 9.8 S25FL129P Status Register Bit Function 1 = Protects when W#/ACC is low Status Register Write Disable protection, even when W#/ACC is low ...
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... Configuration Register Out MSB S25FL129P Table 7.1 and Table 7.1 on page Configuration Register Out MSB MSB S25FL129P_00_04 November 2, 2009 for more ...
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... Figure 9.15 Write Registers (WRR) Instruction Sequence – 8 data bits CS# SCK SI SO November 2, 2009 S25FL129P_00_04 Table 9.8 shows the status register bits and their functions. 9.16) bit of data has been latched in. If not, the Write Registers (WRR) instruction is not ...
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... Ready to accept Page Program, Parameter Program, Parameter Sector Erase, Sector Sector Erase, & Sector Erase, and Bulk Erase Erase instructions Protected against Page Ready to accept Page Program, Sector Erase, Program, Sector Erase and Bulk Erase instructions Table 7.3 on page 17. S25FL129P_00_04 November 2, 2009 ...
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... The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see CS# Mode 3 SCK Mode SCK MSB November 2, 2009 S25FL129P_00_04 Figure 9.17 Table 7.3 on page 17). Figure 9.17 Page Program (PP) Command Sequence ...
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... Byte Byte 11 Byte 12 Byte 253 Byte 254 Byte 255 Byte 256 S25FL129P_00_04 November 2, 2009 *MSB ...
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... Note: The P4E and P8E commands do not apply to the uniform 256 KB sector device. Figure 9.19 Parameter Sector Erase (P4E, P8E) Instruction Sequence CS# SCK SI November 2, 2009 S25FL129P_00_04 Table 5.1 on page 12 valid address for the P4E or P8E command. ...
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... Table 7.3 on page 17 valid address for the SE command. CS# must be Figure 9.20 Sector Erase (SE) Command Sequence Command 24 bit Address 23 22 MSB S25FL129P Figure 9.20 . The Status Register may SE Table 7 S25FL129P_00_04 November 2, 2009 and ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see on page 17). Otherwise, the device ignores the command. CS# SCK SI SO November 2, 2009 S25FL129P_00_04 Figure 9.21 Bulk Erase (BE) Command Sequence Mode ...
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... (see Table 16.1 on page 58). DP Section 9.20 and 9.20.1). Figure 9.22 Deep Power-Down (DP) Command Sequence Command Standby Mode S25FL129P Figure 9.22 and Table 9.1 the device enters the DP mode and current DP Deep Power-down Mode S25FL129P_00_04 November 2, 2009 ...
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... Note: The RES command dose not reset the Write Enable Latch (WEL) bit. Figure 9.23 Release from Deep Power-Down (RES) Command Sequence CS# Mode 3 SCK Mode 0 SI Hi-Z SO November 2, 2009 S25FL129P_00_04 after the 8-bit RES command byte. The device transitions RES(max) (see RES 0 2 ...
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... Dummy Bytes Command MSB Deep Power-Down Mode Figure 9.25 Clear Status Register (CLSR) Instruction Sequence Instruction S25FL129P 39 t RES 0 Electronic MSB Standby Mode S25FL129P_00_04 November 2, 2009 , as RES ...
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... SCK Instruction SI High Impedance SO November 2, 2009 S25FL129P_00_04 OTP Regions on page 52 for details on the OTP region. The protocol of the OTP Figure 9.26 OTP Program Instruction Sequence ...
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... OTP memory, as highlighted in Figures Lock Register ESN1 Lock Register ESN2 (Bit 0) (Bit 1h/0h S25FL129P ESN1 Region Contains ESN2 Region Contains 0h 0h Factory/Customer Unique random pattern programmed pattern 10.1 and 10.2. S25FL129P_00_04 November 2, 2009 ...
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... Notes 1. Bit 0 at address 0x100h locks ESN1 region. 2. Bit 1 at address 0x100h locks ESN2 region. 3. Bits 2-7 (“X”) are NOT programmable and will be ignored. November 2, 2009 S25FL129P_00_04 Figure 10.1 OTP Memory Map - Part EGION ...
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... S25FL129P Address B it Locks Region… 0 OTP17 0x214h 1 OTP18 2 OTP19 3 OTP20 4 OTP21 5 OTP22 6 OTP23 7 OTP24 0 OTP25 0x215h 1 OTP26 2 OTP27 3 OTP28 4 OTP29 5 OTP30 OTP31 6 R eserved 7 S25FL129P_00_04 November 2, 2009 ...
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... (cut-off November 2, 2009 S25FL129P_00_04 Table 11.1 on page 56): (min.) plus a period power-up, the device is in standby mode (not Deep Power-Down mode) and PU rail decoupled by a suitable capacitor close to the CC Figure 11 ...
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... Voltage Rise and Fall time CC ACC at V and First command S25FL129P Min Max 2.7 2.4 0.2 2.3 300 1.0 Section 10. on page 52). from Removing Command OK t VHH ). HH Min. Max Unit 8.5 9.5 V 2.2 µs 5 µs S25FL129P_00_04 November 2, 2009 Unit µs µs IH ...
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... Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 15. Operating Ranges Ambient Operating Temperature (T Positive Power Supply Note Operating ranges define those limits between which functionality of the device is guaranteed. November 2, 2009 S25FL129P_00_04 (2) + 0.5V. During voltage transitions inputs or I/Os may overshoot to CC Figure 14 ...
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... GND 25°C and S25FL129P Limits * Min. Typ Max 2.7 3.6 8.5 9.5 -0 min. 0.4 V -0.6 CC ±2 ± 200 CC 80 250 S25FL129P_00_04 November 2, 2009 Table 17.1 Unit µA µ µA µA µA ...
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... 17. Test Conditions Input Levels Symbol C L November 2, 2009 S25FL129P_00_04 Figure 17.1 AC Measurements I/O Waveform 0 0 Table 17.1 Test Specifications Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage ...
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... V/ns V/ (Serial)Δ 9.5 (Dual/Quad)Δ 6.5 (Serial)∞ (Dual/Quad)∞ 7 (Dual/Quad)Ω 1 1.2 2.4 ms 0.5 2 sec 2 8 sec 200 800 ms 128 256 sec 30 µs 10 µs µs µs S25FL129P_00_04 November 2, 2009 ...
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... C IN (applies to SCK, PO7-PO0, SI, CS#) Output Capacitance C OUT (applies to PO7-PO0, SO) CS# t SCK SI Hi-Z SO CS# SCK November 2, 2009 S25FL129P_00_04 Parameter Test Conditions V OUT Figure 18.2 SPI Mode 0 (0,0) Input Timing t CSS CSH SU:DAT CRT ...
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... HOLD# Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 W# CS# SCK SI Hi Figure 18.4 HOLD# Timing HLCH CHHL t CHHH WPS S25FL129P HHCH WPH S25FL129P_00_04 November 2, 2009 ...
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... November 2, 2009 S25FL129P_00_04 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS ...
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... PIN # TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT S25FL129P (ND- 0. SEE DETAIL "A" BOTTOM VIEW 3408\ 16-038.28a S25FL129P_00_04 November 2, 2009 ...
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... 19.3 FAB024 — 24-ball Ball Grid Array ( mm) package November 2, 2009 S25FL129P_00_04 S25FL129P 65 ...
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... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE PACKAGE OUTLINE TYPE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. S25FL129P 3642 F16-038.9 \ 09.10.09 S25FL129P_00_04 November 2, 2009 ...
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... Added FAC024 BGA package DC Characteristics Added Note 1 indicating that I AC Characteristics Added min and max values for Sector Erase Time (256 KB) November 2, 2009 S25FL129P_00_04 Description maximum value only applies to Industrial temperature grade parts ...
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... Section Revision 04 (November 2, 2009) Removed Note 2 Ordering Information Added separate Standby Current values for Industrial and Automotive In-Cabin temperature range parts. DC Characteristics Removed Note Description S25FL129P S25FL129P_00_04 November 2, 2009 ...
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... Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. November 2, 2009 S25FL129P_00_04 ® ...