S25FL128P Meet Spansion Inc., S25FL128P Datasheet
S25FL128P
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S25FL128P Summary of contents
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... Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number S25FL128P_00 S25FL128P Cover Sheet Revision 04 Issue Date July 2, 2007 ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL128P S25FL128P_00_04 July 2, 2007 ...
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... RES command one-byte electronic signature for backward compatibility General Description The S25FL128P is a 3.0 Volt (2 3.6 V), single-power-supply Flash memory device. The device consists of 64 sectors of 256 KB memory, or 256 sectors memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3 ...
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... AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 20.1 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width 20.2 WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL128P S25FL128P_00_04 July 2, 2007 ...
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... Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 19.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 19.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 19.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD July 2, 2007 S25FL128P_00_04 S25FL128P 5 ...
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... S25FL128P Sector Address Table (Uniform 64 KB sector .16 Table 11.1 Manufacturer & Device Identification, RDID (9Fh .23 Table 11.2 READ_ID Command and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 11.3 S25FL128P Status Register (Uniform 256 KB sector .26 Table 11.4 S25FL128P Status Register (Uniform 64 KB sector .27 Table 11.5 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 11.6 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 12.1 ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 13.1 Power-Up Timing Characteristics ...
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... Block Diagram SRAM Logic July 2, 2007 S25FL128P_00_04 Array - L RD DATA PATH IO S25FL128P Array - ...
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... HOLD VCC PO2 PO1 PO0 SO/PO7 8 9 Figure 2.2 8-Pin WSON Package ( mm WSON 3 6 WP#/ACC GND 4 5 S25FL128P SCK SI PO6 PO5 PO4 PO3 GND WP#/ACC VCC HOLD# SCK SI S25FL128P_00_04 July 2, 2007 ...
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... WP#/ACC (Write Protect/Accelerated Programming GND 4. Logic Symbol July 2, 2007 S25FL128P_00_04 I/O Output Transfers data serially out of the device on the falling edge of SCK. Transfers parallel data into the device on the rising edge of SCK or out of Input/Output the device on the falling edge of SCK ...
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... DEVICE FAMILY S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL128P Valid Combinations Table S25FL128P Valid Combinations Package & Model Speed Option Temperature Number 0X MFI, NFI S25FL128P PACKING TYPE ...
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... The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL CPHA Mode Mode July 2, 2007 S25FL128P_00_04 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK SCK SO SI SPI Memory Device ...
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... WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – Page Program (PP The Deep Power Down (DP) command provides additional data protection against 38): S25FL128P S25FL128P_00_04 July 2, 2007 ...
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... Disable (SRWD) bit together provide write protection. Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands consist of a clock pulse count that is a multiple of eight before executing them. Table 7.1 S25FL128P Protected Area Sizes (Uniform 256 KB sector) Status Register Block Protect Bits ...
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... 7.1. Figure 7.1 Hold Mode Operation Hold Condition (standard use) Table 8.2 shows the starting and ending address for each Table 8.1 S25FL128P Device Organization Each Sector has Each Page has 262144 (256 KB sector) 65536 (64 KB sector) 1024 (256 KB sector) 256 (64 KB sector) — ...
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... Table 8.2 S25FL128P Sector Address Table (Uniform 256 KB sector) Sector July 2, 2007 S25FL128P_00_04 Address Range Sector ...
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... Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 255 FF0000h FFFFFFh 254 FE0000h FEFFFFh 253 FD0000h FDFFFFh 252 FC0000h FCFFFFh 251 FB0000h FBFFFFh 250 FA0000h FAFFFFh 249 F90000h F9FFFFh 248 F80000h F8FFFFh 247 F70000h F7FFFFh 246 ...
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... Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 111 6F0000h 6FFFFFh 110 6E0000h 6EFFFFh 109 6D0000h 6DFFFFh 108 6C0000h 6CFFFFh 107 6B0000h 6BFFFFh 106 6A0000h 6AFFFFh 105 690000h 69FFFFh 104 680000h 68FFFFh 103 670000h ...
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... In addition, the WP#/ HH ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result S25FL128P on this pin, the HH HH S25FL128P_00_04 July 2, 2007 ...
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... Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL128P_00_04 Table 11.6 on page 38 lists the complete set of commands the falling edge of SCK. detail the READ command sequence. The first byte specified can be at any Figure 11.1 Read Data Bytes (READ) Command Sequence ...
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... For parallel mode operation, the device requires an Enter Parallel Mode command (55h) before the READ command. An Exit Parallel Mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode Figure 11.2 Parallel Read Instruction Sequence 24-Bit Instruction Address High Impedance S25FL128P Data Out S25FL128P_00_04 July 2, 2007 ...
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... Note that the FAST_READ command is not valid in parallel mode. Figure 11.3 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS# Mode SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL128P_00_04 the falling edge of SCK. Figure 11 ...
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... Instruction Manufacturer / Device Identification High Impedance MSB S25FL128P Extended Device Identification MSB S25FL128P_00_04 July 2, 2007 ...
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... Once in the parallel mode, the flash memory will not exit parallel mode until a Parallel Mode Exit (45h) command is given to the flash device, or upon power down/power up sequence. Figure 11.5 Parallel Read_ID Command Sequence and Data Out Sequence CS# SCK SI PO[7-0] Device Uniform 256 KB Sector Uniform 64 KB Sector July 2, 2007 S25FL128P_00_04 ...
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... Address Manufacturer ID High Impedance MSB S25FL128P Device MSB S25FL128P_00_04 July 2, 2007 23 8 ...
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... Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. SO/PO[7-0] July 2, 2007 S25FL128P_00_04 Figure 11.7 Parallel Read_ID Instruction Sequence ...
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... Figure 11.9 Write Disable (WRDI) Command Sequence CS Mode 3 SCK Mode 0 Command SI Hi-Z SO/PO[7-0] Table 11.3 S25FL128P Status Register (Uniform 256 KB sector) Bit Function 1 = Protects when WP#/ACC is low Status Register Write Disable protection, even when WP#/ACC is low — — — Not used Block Protect 000– ...
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... SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL128P_00_04 Table 11.4 S25FL128P Status Register (Uniform 64 KB sector) Bit Function 1 = Protects when WP#/ACC is low Status Register Write Disable protection, even when WP#/ACC is low — — Block Protect 0000– ...
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... Write Status Register (WRSR) command Command Byte Byte 1 2 S25FL128P 13 14 Byte n Status Register Out Table 7.1 S25FL128P_00_04 July 2, 2007 ...
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... Once in the parallel mode, the flash memory will not exit the parallel mode until a Parallel Mode Exit (45h) command is given to the flash device, or upon power-down or power-up sequence. July 2, 2007 S25FL128P_00_04 Table 11.3, S25FL128P Status Register (Uniform 256 KB sector) on page 26 Figure 11.12 Write Status Register (WRSR) Command Sequence CS Mode 3 ...
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... Note) (See Note) Ready to accept Page Protected against program Program and Sector Erase and erase commands commands Ready to accept Page Protected against program Program and Sector Erase and erase commands commands Table 7.1 on page 13. . The Status Register may PP S25FL128P_00_04 July 2, 2007 ...
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... CS# Mode 3 SCK Mode SCK MSB July 2, 2007 S25FL128P_00_04 Figure 11.14 Page Program (PP) Command Sequence 24-Bit Address Command MSB ...
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... Figure 11.15 Parallel Page Program (PP) Instruction Sequence Instruction (02h) Address Byte MSB 90h High-Z S25FL128P Address Address Byte 2 Byte Byte Byte Byte S25FL128P_00_04 July 2, 2007 n Hi-Z ...
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... The device does not execute an SE command that specifies a sector that is protected by the Block Protect bits (see Table 7.1 on page CS# Mode 3 SCK Mode 0 SI Hi-Z SO/PO[7-0] July 2, 2007 S25FL128P_00_04 Table 7.1 on page 13 valid address for the SE command. CS# must be 13). Figure 11.16 Sector Erase (SE) Command Sequence ...
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... Otherwise, the device ignores the command. SO/PO[7- Figure 11.17 Bulk Erase (BE) Command Sequence CS# Mode SCK Mode 0 Command SI Hi-Z S25FL128P Figure 11.17 and Table 11.6. . The Status Register may BE Table 7 S25FL128P_00_04 July 2, 2007 ...
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... The device rejects any DP command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. CS# Mode 3 SCK Mode 0 SI Hi-Z SO/PO[7-0] July 2, 2007 S25FL128P_00_04 DP, (see Table 17.1 on page 41). 11.13 and 11.14). ...
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... after the 8-bit RES command byte. The device transitions RES(max) (see RES Mode 3 Mode 0 Command SI Hi-Z Deep Power-down Mode S25FL128P Figure 11.19 and Table 11.6. Table 19.1 on page 42). In the standby mode RES Standby Mode Figure 11.20 S25FL128P_00_04 July 2, 2007 and ...
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... To release the device from Deep Power Down and read Electronic ID in parallel mode, a Parallel Mode Enter command (55h) must be issued before the RES command. The device will not exit parallel mode until a Parallel Mode Exit command (45h) is written, or upon power-down or power-up sequence. 3. Byte 1 will output the Electronic Signature. July 2, 2007 S25FL128P_00_04 ...
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... Removing VHH Command OK Min. Max. Unit 8.5 9.5 V 250 S25FL128P_00_04 July 2, 2007 ...
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... Initial Delivery State The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status Register contains 00h (all Status Register bits are 0). July 2, 2007 S25FL128P_00_04 Table 13 ...
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... Figure 15.2 Maximum Positive Overshoot Waveform + Table 16.1 Operating Ranges Description ) Industrial A Voltage Range S25FL128P Rating –65°C to +150°C –0 +0 –2.0 V for periods Rating –40°C to +85°C 2 3.6 V S25FL128P_00_04 July 2, 2007 ...
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... Output High Voltage OH Note Typical values are 18. Test Conditions 0.8 V Input Levels 0.2 V Symbol C L July 2, 2007 S25FL128P_00_04 Table 17.1 DC Characteristics (CMOS Compatible) Test Conditions (See Note) SCK = 0 0.9V 104 MHz (Serial MHz (Serial: Fast SCK = 0 ...
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... S25FL128P_00_04 July 2, 2007 Unit MHz MHz V/ns V/ µs µs ...
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... CS# t CSH SCK SI Hi-Z SO CS# SCK July 2, 2007 S25FL128P_00_04 Figure 19.1 SPI Mode 0 (0,0) Input Timing t CSS SU:DAT CRT HD:DAT t CFT MSB IN Figure 19.2 SPI Mode 0 (0,0) Output Timing S25FL128P t CS ...
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... SO SI HOLD# Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP#/ACC CS# SCK Figure 19.3 HOLD# Timing WPS Hi-Z S25FL128P WPH S25FL128P_00_04 July 2, 2007 ...
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... July 2, 2007 S25FL128P_00_04 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS ...
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... PIN # TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT S25FL128P D2 D2 E2 (ND- 0. SEE DETAIL "A" BOTTOM VIEW 3408\ 16-038.28a S25FL128P_00_04 July 2, 2007 K B ...
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... Section Revision 01 (January 12, 2007) Initial release. Revision 02 (March 13, 2007) Distinctive Characteristics Changed standby mode current. S25FL128P Sector Address Table Corrected addresses for sectors 0 and 32. (Uniform 64 KB sector) Parallel Mode (for 16-pin SO package Added last sentence in section. only) Read Status Register (RDSR: 05h) Separated status register bit descriptions into an additional subsection ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion Logo, MirrorBit , MirrorBit S25FL128P ® ™ ™ ™ Eclipse , ORNAND , HD-SIM and S25FL128P_00_04 July 2, 2007 ...