S25FL016A Meet Spansion Inc., S25FL016A Datasheet
S25FL016A
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S25FL016A Summary of contents
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... Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number S25FL016A_00 Revision C Amendment 3 S25FL016A Cover Sheet Issue Date January 7, 2008 ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL016A S25FL016A_00_C3 January 7, 2008 ...
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... Manufactured on 0.20 µm MirrorBit process technology General Description The S25FL016A is a 3.0 Volt (2 3.6 V), single-power-supply Flash memory device. The device consists of thirty-two sectors, each with 512 Kb memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3 ...
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... SOC008 wide—8-pin Plastic Small Outline Package (208 mils Body Width 17.2 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width 17.3 WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL016A S25FL016A_00_C3 January 7, 2008 ...
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... Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD January 7, 2008 S25FL016A_00_C3 S25FL016A 5 ...
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... Tables Table 5.1 S25FL016A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 7.1 S25FL016A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 8.1 S25FL016A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 8.2 S25FL016A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 9.1 Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 9.2 S25FL016A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 9.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 9.4 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 10.1 Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 12.1 Absolute Maximum Ratings ...
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... Block Diagram SRAM Logic 2. Connection Diagrams January 7, 2008 S25FL016A_00_C3 Array - L RD DATA PATH IO Figure 2.1 16-pin Plastic Small Outline Package (SO) 16 HOLD VCC CS S25FL016A Array - SCK ...
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... Figure 2.2 8-pin Plastic Small Outline Package (SO CS GND Figure 2 8-Pin WSON Package ( mm WSON GND 5 S25FL016A VCC HOLD# SCK SI VCC HOLD# SCK SI S25FL016A_00_C3 January 7, 2008 ...
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... V Input CC GND Input 4. Logic Symbol January 7, 2008 S25FL016A_00_C3 Description Signal Data Output: Transfers data serially out of the device on the falling edge of SCK. Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data the rising edge of SCK. ...
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... DEVICE FAMILY S25FL ® Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL016A Valid Combinations Table S25FL016A Valid Combinations Package & Speed Option Temperature MAI, MFI 0L NAI, NFI S25FL016A PACKING TYPE (Note ...
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... The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL CPHA Mode Mode January 7, 2008 S25FL016A_00_C3 Figure 6.2 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK SCK SO SI ...
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... Status Register The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.2, S25FL016A Status Register on page Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. ...
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... If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. January 7, 2008 S25FL016A_00_C3 Table 7.1 S25FL016A Protected Area Sizes Memory Array Protected Protected Address Range Sectors ...
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... Figure 7.1 Hold Mode Operation Hold Condition (standard use) (non-standard use) Table 8.2 shows the starting and ending address for each Table 8.1 S25FL016A Device Organization Each Sector has Each Page has 65,536 256 256 — — — S25FL016A ...
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... SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 January 7, 2008 S25FL016A_00_C3 Table 8.2 S25FL016A Sector Address Table Address Range 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h ...
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... Figure 9.1 Read Data Bytes (READ) Command Sequence Command 24-Bit Address MSB S25FL016A ) presented SCK Data Out 1 Data Out MSB S25FL016A_00_C3 January 7, 2008 ...
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... Driving CS# high at any time during data output also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. January 7, 2008 S25FL016A_00_C3 Figure 9 ...
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... Write Enable Latch (WEL) bit which Figure 9.4 Write Enable (WREN) Command Sequence Mode 3 Mode 0 Command Hi-Z S25FL016A Device Identification Device Identification Memory Capacity 02h 14h S25FL016A_00_C3 January 7, 2008 ...
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... Mode 3 SCK Mode 0 Command SI Hi-Z SO Figure 9.6 Table 9.2 S25FL016A Status Register Bit Function 1 = Protects when W# is low Status Register Write Disable protection, even when W# is low — Not used — Not used 000–111 = Protects upper half of address range in 5 sizes. See Block Protect Table 7 ...
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... Command MSB Status Register Out Table 9.2, S25FL016A Status Register on page 19 S25FL016A 15 14 MSB Status Register Out Table 7.1 shows the status register Table 9.3 on page 21 shows that W# must S25FL016A_00_C3 January 7, 2008 ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see January 7, 2008 S25FL016A_00_C3 Figure 9.7 Write Status Register (WRSR) Command Sequence ...
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... S25FL016A Data Byte MSB Data Byte 256 MSB Figure 9.9 . The Status Register may 24-bit Address S25FL016A_00_C3 January 7, 2008 and ...
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... DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. January 7, 2008 S25FL016A_00_C3 Figure 9 ...
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... RES command byte. The device transitions RES(max) (see Table 16.1 on page RES Command Deep Power-down Mode S25FL016A t DP Deep Power-down Mode Figure 9.12 and Table 9.4 on page 25. 29). In the standby mode RES Standby Mode S25FL016A_00_C3 January 7, 2008 ...
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... WRSR DP Power Saving RES Notes 1. The S25FL016A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (14h). 2. The S25FL016A has an Electronic Signature ID of 14h. January 7, 2008 S25FL016A_00_C3 for the command sequence and signature value. The Electronic ...
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... Figure 10.1 Power-Up Timing Diagram V cc (max) (min Table 10.1 Power-Up Timing Characteristics Parameter V (minimum (min) to device operation CC S25FL016A reaches the allowable values as follows CC rises to the threshold at power-down, all CC Full Device Access Time Min Max 2.7 10 S25FL016A_00_C3 January 7, 2008 CC feed. Unit V ms ...
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... Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 13. Operating Ranges Ambient Operating Temperature (T Positive Power Supply Note Operating ranges define those limits between which functionality of the device is guaranteed. January 7, 2008 S25FL016A_00_C3 Operating Ranges section of this document is not implied. Device Table 12.1 Absolute Maximum Ratings Description 12 ...
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... 0.4 CC min V – 0 Input and Output Timing Reference levels Min Max S25FL016A_00_C3 January 7, 2008 Unit µA µA µA µ Unit ...
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... Bulk Erase Time BE Notes 1. Typical program and erase times assume the following conditions: 25° Under worst-case conditions of 90° Not 100% tested January 7, 2008 S25FL016A_00_C3 Table 16.1 AC Characteristics Parameter = 3.0V; 10,000 cycles; checkerboard data pattern CC = 2.7V; 100,000 cycles ...
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... Figure 16.1 SPI Mode 0 (0,0) Input Timing t CSS SU:DAT CRT HD:DAT t CFT MSB IN Figure 16.2 SPI Mode 0 (0,0) Output Timing Figure 16.3 HOLD# Timing S25FL016A CSH CSS LSB DIS LSB OUT t LZ S25FL016A_00_C3 January 7, 2008 ...
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... Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi-Z SO January 7, 2008 S25FL016A_00_C3 WPS S25FL016A t WPH 31 ...
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... THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED FROM THE SEATING PLANE. S25FL016A WITH PLATING (b) BASE 7 METAL SECTION A 0.07 R MIN. GAUGE PLANE A SEATING PLANE DETAIL B 3432 \ 16-038.03 \ 10.28.04 S25FL016A_00_C3 January 7, 2008 ...
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... January 7, 2008 S25FL016A_00_C3 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, MAX PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0 ...
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... PIN # TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT S25FL016A (ND- SEE DETAIL "A" BOTTOM VIEW 3408\ 16-038.28a S25FL016A_00_C3 January 7, 2008 ...
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... Added overshoot and undershoot information. Revision C2 (June 29, 2007) Device Operations Added sentence to Byte or Page Programming Revision C3 (January 7, 2008) Ordering Information Added Tray packing option for 8-pin and 16-pin SOIC packages. January 7, 2008 S25FL016A_00_C3 Description specifications. W CC2 S25FL016A ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion Logo, MirrorBit , MirrorBit S25FL016A S25FL016A_00_C3 January 7, 2008 ® ™ ™ ™ Eclipse , ORNAND , HD-SIM ...