S25FL008A Meet Spansion Inc., S25FL008A Datasheet
S25FL008A
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S25FL008A Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL008A_00 Notice On Data Sheet Designations Revision B Amendment 2 S25FL008A Cover Sheet for definitions. Issue Date June 29, 2007 ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL008A S25FL008A_00_B2 June 29, 2007 ...
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... Manufactured on 0.20 µm MirrorBit process technology General Description The S25FL008A is a 3.0 Volt (2 3.6 V), single-power-supply Flash memory device. The device consists of 16 sectors, each with 512 Kb memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3 ...
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... Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 15. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17.1 SOC 008 wide—8-pin Plastic Small Outline 208 mils Body Width Package . . . . . . . . . . . . . 30 17.2 USON mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 18. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL008A S25FL008A_00_B2 June 29, 2007 ...
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... Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.2 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16.5 Write Protect Setup and Hold Timing during WRSR when SRWD June 29, 2007 S25FL008A_00_B2 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 S25FL008A 5 ...
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... Tables Table 5.1 S25FL008A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 7.1 S25FL008A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 8.1 S25FL008A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 8.2 S25FL008A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9.1 Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 9.2 S25FL008A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 9.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 9.4 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 10.1 Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 12.1 Absolute Maximum Ratings ...
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... Block Diagram SRAM Logic 2. Connection Diagrams June 29, 2007 S25FL008A_00_B2 Array - L RD DATA PATH IO Figure 2.1 8-pin Plastic Small Outline Package (SO GND Figure 2.2 8L USON ( CS GND 4 5 S25FL008A ...
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... Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Supply Voltage Ground SCK CS# W# HOLD# GND S25FL008A SO S25FL008A_00_B2 June 29, 2007 ...
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... PACKAGE TYPE M N SPEED 0L DEVICE TECHNOLOGY A DENSITY 008 = DEVICE FAMILY S25FL TM Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL008A Valid Combinations Table S25FL008A Valid Combinations Package & Model Speed Option Temperature Number MAI, MFI 0L NAI, NFI S25FL008A (Note 1) = Tray ...
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... SO SI SCK SCK SO SI SCK SO SI SPI Memory Device CS# W# HOLD# CS# Figure 6.2 SPI Modes Supported CS# SCK SCK MSB SI SO S25FL008A Figure 6.2 for each of the two modes: SCK SO SI SPI Memory SPI Memory Device Device W# HOLD# CS# W# HOLD# MSB S25FL008A_00_B2 June 29, 2007 ...
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... Status Register The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.2, S25FL008A Status Register on page Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. ...
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... If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low Table 7.1 S25FL008A Protected Area Sizes Memory Array Protected Protected Address Range Sectors ...
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... Condition (standard use) Table 8.2 shows the starting and ending address for each Table 8.1 S25FL008A Device Organization Each Sector has Each Page has 65,536 256 — Table 8.2 S25FL008A Sector Address Table Address Range F0000h E0000h D0000h C0000h B0000h A0000h 90000h 80000h 70000h ...
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... Figure 9.1 Read Data Bytes (READ) Command Sequence Command 24-Bit Address MSB S25FL008A ) presented SCK Data Out 1 Data Out MSB S25FL008A_00_B2 June 29, 2007 ...
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... Driving CS# high at any time during data output also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. June 29, 2007 S25FL008A_00_B2 Figure 9 ...
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... Write Enable Latch (WEL) bit which Figure 9.4 Write Enable (WREN) Command Sequence CS Mode 3 SCK Mode 0 Command SI Hi-Z SO S25FL008A Device Identification Device Identification Memory Capacity 02h 13h S25FL008A_00_B2 June 29, 2007 ...
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... Mode 3 SCK Mode 0 Command SI Hi-Z SO Figure 9.6 Table 9.2 S25FL008A Status Register Bit Function 1 = Protects when W# is low Status Register Write Disable protection, even when W# is low — Not used — Not used 000–111 = Protects upper half of address range in 5 sizes. See Block Protect Table 7 ...
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... Command MSB Status Register Out Table 9.2, S25FL008A Status Register on page 17 S25FL008A 15 14 MSB Status Register Out Table 7.1 shows the status register Table 9.3 on page 19 shows that W# must S25FL008A_00_B2 June 29, 2007 ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see June 29, 2007 S25FL008A_00_B2 Figure 9.7 Write Status Register (WRSR) Command Sequence ...
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... S25FL008A Data Byte MSB Data Byte 256 MSB Figure 9.9 . The Status Register may 24-bit Address S25FL008A_00_B2 June 29, 2007 and ...
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... DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. June 29, 2007 S25FL008A_00_B2 Figure 9 ...
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... RES command byte. The device transitions RES(max) (see RES Mode 3 Mode 0 Command Hi-Z Deep Power-down Mode S25FL008A t DP Deep Power-down Mode Figure 9.12 and Table 9.4 on page 23. Table 16.1 on page 27). In the standby mode RES Standby Mode S25FL008A_00_B2 June 29, 2007 ...
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... WRSR DP Power Saving RES Notes 1. The S25FL008A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (13h). 2. The S25FL008A has an Electronic Signature ID of 13h. June 29, 2007 S25FL008A_00_B2 for the command sequence and signature value. The Electronic ...
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... Figure 10.1 Power-Up Timing Diagram V cc (max) cc (min Table 10.1 Power-Up Timing Characteristics Parameter V (minimum (min) to device operation CC S25FL008A reaches the allowable values as follows CC rises to the threshold at power-down, all CC Full Device Access Time Min Max 2.7 10 S25FL008A_00_B2 June 29, 2007 CC feed. Unit V ms ...
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... This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in on page 26, when relying on the quoted parameters. June 29, 2007 S25FL008A_00_B2 Operating Ranges section of this document is not implied. Device Table 12 ...
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... 0.4 CC min V – 0 Input and Output Timing Reference levels Min Max S25FL008A_00_B2 June 29, 2007 Unit µA µA µA µ Unit ...
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... Bulk Erase Time BE Notes 1. Typical program and erase times assume the following conditions: 25° Under worst-case conditions of 90° Not 100% tested June 29, 2007 S25FL008A_00_B2 Figure 16.1 AC Characteristics Parameter = 3.0 V; 10,000 cycles; checkerboard data pattern CC = 2.7 V; 100,000 cycles ...
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... Figure 16.2 SPI Mode 0 (0,0) Input Timing t CSS SU:DAT CRT HD:DAT t CFT MSB IN Figure 16.3 SPI Mode 0 (0,0) Output Timing Figure 16.4 HOLD# Timing S25FL008A CSH CSS LSB DIS LSB OUT S25FL008A_00_B2 June 29, 2007 ...
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... Figure 16.5 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi-Z SO June 29, 2007 S25FL008A_00_B2 WPS S25FL008A t WPH 29 ...
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... THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED FROM THE SEATING PLANE. S25FL008A WITH PLATING (b) BASE 7 METAL SECTION A 0.07 R MIN. GAUGE PLANE A SEATING PLANE DETAIL B 3432 \ 16-038.03 \ 10.28.04 S25FL008A_00_B2 June 29, 2007 ...
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... BSC A 0.45 0.50 A1 0.00 0.02 K 0.20 MIN. θ 0 --- June 29, 2007 S25FL008A_00_B2 NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTE 2. ALL DIMENSIONS ARE IN MILLIMETERS DEGREES THE TOTAL NUMBER OF TERMINALS DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS 5 MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. ...
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... Rewrote entire document for better flow and clarity. No specifications were changed. Revision B1 (February 19, 2007) Absolute Maximum Ratings Added overshoot/undershoot spec Operating Ranges Removed commercial option Revision B2 (June 29, 2007) Device Operations Added a sentence to Byte or Page Programming Description S25FL008A S25FL008A_00_B2 June 29, 2007 . CC2 ...
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... Copyright © 2004-2007 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. June 29, 2007 S25FL008A_00_B2 ® ...