NJU26203 New Japan Radio Co.,Ltd, NJU26203 Datasheet - Page 8

• Manufacturer Part Number: NJU26203
• Description: Nju26203 Dolby Pro Logic Ii Decoder
• Manufacturer: New Japan Radio Co.,Ltd

NJU26203
Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
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data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance.
Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
Note:
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up
resistance.
I
4-Wire Serial Interface
2
C Bus
When the NJU26203 is configured for I
Both “ Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” data transfer rate are supported.
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
SSb
SCK
SDIN
SDOUT
Table 6 I
bit7
0
0
0
0
2
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
C Bus Interface Slave address
unstable
Start
bit
bit6
MSB
bit7
bit7
0
0
0
0
bit6
bit6
bit5
Fig. 7 4-Wire Serial Interface Timing
1
1
1
1
Slave Address ( 7bit )
2
C bus communication in SEL=”Low”, the serial host interface transfers
bit5
bit5
bit4
1
1
1
1
bit3
1
1
1
1
bit1
bit1
AD2
bit2
0
0
1
1
LSB
bit0
bit0
R/W
bit
AD1
bit1
unstable
0
1
0
1
ACK
R/W
R/W
bit0
Ver.2007-02-28