cs4382 Cirrus Logic, Inc., cs4382 Datasheet - Page 30

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cs4382

Manufacturer Part Number
cs4382
Description
114 Db, 192 Khz 8-channel D/a Converter
Manufacturer
Cirrus Logic, Inc.
Datasheet

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30
7.1
7.2
7.3
7.3.1
7.3.2
7.4
Enabling the Control Port
On the CS4382 the control port pins are shared with stand-alone configuration pins. To enable the control
port, the user must set the CPEN bit. This is done by performing a I²C or SPI write. Once the control port is
enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts, the CPEN bit (see Section 4.1.1) should be set prior to the completion of the
Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone
power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any
time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed
can cause audible artifacts.
Format Selection
The control port has 2 formats: SPI and I²C, with the CS4382 operating as a slave device.
If I²C operation is desired, AD0/CS should be tied to VLC or GND. If the CS4382 ever detects a high to low
transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
I²C Format
In I²C Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL,
with a clock to data relationship as shown in Figure 7. The receiving device should send an acknowledge
(ACK) after each byte received. There is no CS pin. Pin AD0 forms the partial chip address and should be
tied to VLC or GND as required. The upper 6 bits of the 7 bit address field must be 001100.
Note:
SPI Format
In SPI format, CS is the CS4382 chip select signal, CCLK is the control port bit clock, CDIN is the input data
line from the microcontroller and the chip address is 0011000. CS, CCLK and CDIN are all inputs and data
is clocked in on the rising edge of CCLK.
Note:
Writing in I²C Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address
Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS4382 to ac-
knowledge between each byte. To end the transaction, send a STOP condition.
Reading in I²C Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.
MCLK is required during all I²C transactions. Please see
tional information on the I²C Bus specification or visit http://www.semiconductors.philips.com.
The CS4382 is write-only when in SPI format.
“References” on page 40
to obtain addi-
CS4382
DS514F2

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