ad5324-ep Analog Devices, Inc., ad5324-ep Datasheet
ad5324-ep
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ad5324-ep Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. 2 5.5 V, 500 μA, Quad Voltage Output 12-Bit DAC in 10-Lead Package GENERAL DESCRIPTION The AD5324- 10-lead MSOP package that operates from a single 2 5.5 V supply, consuming 500 μ Its on-chip output amplifiers allows rail-to-rail output swing to be achieved with a slew rate of 0.7 V/μ ...
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... AD5324-EP TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Characteristics ........................................................................ 4 REVISION HISTORY 4/10—Revision 0: Initial Version Timing Characteristics .................................................................5 Absolute Maximum Ratings ............................................................6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions ..............................7 Typical Performance Characteristics ..............................................8 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11 Rev Page ...
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... V 600 900 μA 500 700 μA 0.2 1 μA 0.08 1 μA Rev Page AD5324- unless otherwise noted. MIN MAX Conditions/Comments Guaranteed monotonic by design over all codes See Figure 2 See Figure 2 Lower dead band exists only if offset error is negative ΔV = ±10 kΩ to GND or V ...
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... AD5324-EP AC CHARACTERISTICS kΩ to GND Table 2. Parameter 1 Output Voltage Settling Time Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion 1 Guaranteed by design and characterization, not production tested. 2 Temperature range (S Version): −55°C to +125°C; typical at +25°C. ...
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... DB0 Figure 2. Serial Interface Timing Diagram Rev Page AD5324-EP Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge ...
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... AD5324-EP ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. 1 Parameter Rating V to GND –0 Digital Input Voltage to GND –0 Reference Input Voltage to GND –0 through GND –0 OUT OUT Operating Temperature Range Industrial (EP Version) – ...
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... SCLK 2 9 OUT AD5324- DIN 3 8 OUT TOP VIEW (Not to Scale GND 4 7 OUT REFIN OUT Figure 3. MSOP Pin Configuration th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write Rev Page AD5324- ...
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... AD5324-EP TYPICAL PERFORMANCE CHARACTERISTICS 25° –4 –8 –12 0 500 1000 1500 2000 2500 CODE Figure 4. Typical INL Plot 1 25° 0.5 0 –0.5 –1.0 0 500 1000 1500 2000 2500 CODE Figure 5. Typical DNL Plot 0.8 0.7 0.6 GAIN ERROR 0.5 0.4 0.3 0.2 0.1 OFFSET ERROR 0 – ...
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... Figure 13. Supply Current vs. Logic Input Voltage T = 25° REF CH1 CH2 5.0 5.5 Figure 14. Half-Scale Settling (¼ to ¾ Scale Code Change 25° REF CH1 CH2 5.0 5.5 Rev Page AD5324-EP = 25° 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 V (V) LOGIC = OUT SCLK CH1 1V, CH2 5V, TIME BASE = 1µ ...
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... AD5324- 25° REF V A CH1 OUT CH2 SCLK CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV Figure 16. Exiting Power-Down to Midscale 300 350 400 450 500 I (µA) DD Figure 17. I Histogram with and 2.50 2.49 2.48 2.47 1µs/DIV Figure 18. Major-Code Transition Glitch Energy ...
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... PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.15 0.33 SEATING 0.23 0.05 PLANE 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 22. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Package Description 10-Lead Mini Small Outline Package (MSOP) Rev Page 0.80 8° 0.60 0° 0.40 Package Option RM-10 AD5324-EP Branding DFT ...
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... AD5324-EP NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08971-0-4/10(0) Rev Page ...