ad5065bruz-1reel7 Analog Devices, Inc., ad5065bruz-1reel7 Datasheet

ad5065bruz-1reel7

Manufacturer Part Number

ad5065bruz-1reel7

Description

Fully Accurate 12-/14-/16-bit Vout Dac Spi Interface 2.7 V To 5.5 V In A Tssop

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD5065BRUZ-1REEL7.pdf (33 pages)

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Preliminary Technical Data

FEATURES

Low power Dual 12-/14-/16 bit DAC, ± 1LSB INL

Individual Voltage reference pins

Rail-to-rail operation

2.7 V to 5.5 V power supply

Power-on reset to zero scale or midscale

Power down to 400 nA @ 5 V, 200 nA @ 3 V

3 power-down functions

Per channel power-down

Low glitch upon power up

Hardware Power Down lock Out Capability

Hardware LDAC with LDAC override function

CLR Function to programmable code

SDO daisy-chaining option

14 lead TSSOP

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5025/45/65 are low power, dual 12-/14-/16-bit buffered

voltage-out DACs offering relative accuracy specs of 1 LSB INL

with individual reference pins and can operate from a single 2.7

V to 5.5 V supply. The AD5025/45/65 64 parts also offer a

differential accuracy specification of ±1 LSB. The parts use a

versatile 3-wire, low power Schmitt trigger serial interface that

operates at clock rates up to 50 MHz and is compatible with

standard SPI®, QSPI™, MICROWIRE™, and DSP interface

standards. The reference for the AD5025/45 and AD5065 are

supplied from an external pin. A reference buffer is also

provided on-chip. The AD5025/45/64 incorporates a power-on

reset circuit that ensures the DAC output powers up zero scale

or midscale and remains there until a valid write takes place to

the device. The AD5025/45/65 contain a power-down feature

that reduces the current consumption of the device to typically

330 nA at 5 V and provides software selectable output loads

while in power-down mode. The parts are put into power-down

mode over the serial interface. Total unadjusted error for the

parts is <2 mV.

Both parts exhibit very low glitch on power-up. The outputs of

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Fully Accurate 12-/14-/16-Bit V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

Functional Block Diagrams

SYNC

Table 1. Related Devices

Part No.

AD5666

AD5066

AD5064/44/24

AD5063/62

AD5061

AD5060/40

all DACs can be updated simultaneously using the LDAC

function, with the added functionality of user-selectable DAC

channels to simultaneously update. There is also an

asynchronous CLR that clears all DACs to a software-selectable

code—0 V, midscale, or full scale. The Part also features a power

down lockout pin PDL , which can be used to prevent the DAC

from entering power down under any circumstances over the

serial interface.

PRODUCT HIGHLIGHTS

SCLK

SDO

PDL

DIN

Dual channel available in 14-lead TSSOP package with

individual Voltage reference pins.

12-/14-/-16 bit accurate, 1 LSB INL.

Low glitch on power-up.

High speed serial interface with clock speeds up to 50 MHz.

Three power-down modes available to the user.

Reset to known output voltage (zero scale or midscale).

Power Down lockout capability.

INTERFACE

LDAC

LOGIC

CLR

LDAC

AD5025/AD5045R/AD5065

Description

Quad,16-bit buffered D/A,16 LSB INL, TSSOP

Quad,16-bit unbuffered D/A,1 LSB INL, TSSOP

Quad 16-bit nanoDAC, 1 LSB INL, TSSOP

16-bit nanoDAC, 1 LSB INL, MSOP

16-/14bit nanoDAC, 4 LSB INL, SOT-23

16-/14bit nanoDAC, 1 LSB INL, SOT-23

INPUT

Figure 1.AD5025/45/65

2.7 V to 5.5 V in a TSSOP

OUT

DAC

GND

AD5025/45/65

DAC SPI Interface

POWER-ON

REFA

RESET

DAC A

DAC B

POR

REFB

BUFFER

www.analog.com

POWER-DOWN

LOGIC

OUT

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ad5065bruz-1reel7 Summary of contents

Page 1

... Quad,16-bit buffered D/A,16 LSB INL, TSSOP Quad,16-bit unbuffered D/A,1 LSB INL, TSSOP Quad 16-bit nanoDAC, 1 LSB INL, TSSOP 16-bit nanoDAC, 1 LSB INL, MSOP 16-/14bit nanoDAC, 4 LSB INL, SOT-23 16-/14bit nanoDAC, 1 LSB INL, SOT-23 www.analog.com © 2007 Analog Devices, Inc. All rights reserved OUT V B OUT ...

Page 2

AD5025/45/65 TABLE OF CONTENTS REVISION HISTORY Preliminary Technical Data Rev. PrB | Page ...

Page 3

Preliminary Technical Data SPECIFICATIONS kΩ to GND unless otherwise noted. MAX Table 2. Parameter Min STATIC PERFORMANCE 2 Resolution Relative Accuracy Differential ...

Page 4

AD5025/45/65 Parameter Min Input Low Voltage, V INL Input High Voltage INH Pin Capacitance LOGIC OUTPUTS (SDO) 3 Output Low Voltage Output High Voltage − High Impedance Leakage Current High Impedance ...

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Preliminary Technical Data AC CHARACTERISTICS kΩ to GND unless otherwise noted. Table Parameter Min Output Voltage Settling Time Output Voltage Settling Time Slew Rate ...

Page 6

AD5025/45/65 TIMING CHARACTERISTICS All input signals are specified with ns/V (10 Figure 2 5.5 V. All specifications T DD Table 4. Limit ...

Page 7

Preliminary Technical Data SCLK SYNC t 8 DIN DB31 INPUT WORD FOR DAC N SDO LDAC Figure 3. Serial Write Operation DB0 DB31 INPUT WORD FOR DAC ...

Page 8

AD5025/45/65 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter Rating V to GND −0 Digital Input Voltage to GND −0 GND −0 ...

Page 9

Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This ...

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AD5025/45/65 TYPICAL PERFORMANCE CHARACTERISTICS TBD Figure 6. INL TBD Figure 7. DNL TBD Figure 8. TUE Preliminary Technical Data Rev. PrB | Page ...

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Preliminary Technical Data TBD Figure 9. INL vs. Reference Input Voltag TBD Figure 10. DNL vs. Reference Input Voltage TBD Figure 11. TUE vs. Reference Input Voltage Rev. PrB | Page AD5025/45/65 ...

Page 12

AD5025/45/65 TBD Figure 12. Gain Error and Full-Scale Error TBD Figure 13. Offset Error vs. Temperature TBD Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage vs. Temperature Rev. PrB | Page Preliminary Technical Data ...

Page 13

Preliminary Technical Data TBD Figure 15. Zero-Scale Error and Offset Error vs. Supply Voltage TBD Figure 16. I Histogram V DD TBD Figure 17. I Histogram 3 5 Rev. PrB | Page ...

Page 14

AD5025/45/65 Figure 18. Headroom at Rails vs. Source and Sink TBD Figure 19. Source and Sink Current Capability with V TBD Figure 20. Source and Sink Current Capability with Rev. PrB ...

Page 15

Preliminary Technical Data TBD Figure 21. Supply Current vs. Code TBD Figure 22. Supply Current vs. Temperature TBD Figure 23. Supply Current vs. Supply Voltage Rev. PrB | Page AD5025/45/65 ...

Page 16

AD5025/45/65 Figure 24. Supply Current vs. Logic Input Voltage Figure 25. Full-Scale Settling Time TBD Figure 26. Power-On Reset Preliminary Technical Data Rev. PrB | Page ...

Page 17

Preliminary Technical Data TBD Figure 27. Power-On Reset to Midscale TBD Figure 28. Exiting Power-Down to Midscale TBD Figure 29. Digital-to-Analog Glitch Impulse (See Figure 34) Rev. PrB | Page AD5025/45/65 ...

Page 18

AD5025/45/65 TBD Figure 30. Analog Crosstalk TBD Figure 31. DAC-to-DAC Crosstalk TBD Figure 32. 0 Output Noise Plot Preliminary Technical Data Rev. PrB | Page ...

Page 19

Preliminary Technical Data TBD Figure 33. Typical Supply Current vs. Frequency @ 5.5 V TBD Figure 34. Digital-to-Analog Glitch Energy TBD Figure 35. Noise Spectral Density, Internal Reference 1 Rev. PrB | Page AD5025/45/65 ...

Page 20

AD5025/45/65 TBD Figure 36. Total Harmonic Distortion TBD Figure 37. Settling Time vs. Capacitive Load TBD Figure 38. Hardware CLR TBD Figure 39. Multiplying Bandwidth Preliminary Technical Data Rev. PrB | Page ...

Page 21

Preliminary Technical Data TBD Figure 40.Typical output slew rate Rev. PrB | Page AD5025/45/65 ...

Page 22

AD5025/45/65 THEORY OF OPERATION D/A SECTION The AD5025/45/65 are single 12-/14 and 16-bit, serial input, voltage output DACs. The parts operate from supply voltages of 2 5.5 V. Data is written to the AD5025/45/ 32-bit word ...

Page 23

Preliminary Technical Data Table 8. Address Commands Address ( Selected DAC Channel DAC A DAC B ...

Page 24

AD5025/45/65 INPUT SHIFT REGISTER The AD5025/45/65 input shift register is 32 bits wide (see Figure 43). The first four bits are don’t cares. The next four bits are the command bits (see Table 8), followed by the ...

Page 25

Preliminary Technical Data DAISY-CHAINING For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin can be used to daisy-chain several devices together and provide serial read-back. The ...

Page 26

AD5025/45/65 When both Bit DB9 and Bit DB8, in the control register are set to 0, the part works normally with its normal power consumption of TBD However, for the three power-down modes, the supply current falls ...

Page 27

Preliminary Technical Data Table 9. DCEN (Daisy-Chain Enable) Register (DB1 Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function MSB DB31 to DB28 DB27 DB26 DB25 Don’t cares Command ...

Page 28

AD5025/45/65 CLEAR CODE REGISTER The AD5025/45/65 has a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers ...

Page 29

Preliminary Technical Data Table 13. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF operation Table 14. 32-Bit Input Shift Register Contents for Clear ...

Page 30

AD5025/45/65 MICROPROCESSOR INTERFACING AD5025/45/65 to Blackfin® ADSP-BF53X Interface Figure 48 shows a serial interface between the AD5025/45/65 and the Black fin ADSP-BF53X microprocessor. The ADSP- BF53X processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and ...

Page 31

Preliminary Technical Data APPLICATIONS USING A REFERENCE AS A POWER SUPPLY FOR THE AD5025/45/65 Because the supply current required by the AD5025/45/65 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to ...

Page 32

AD5025/45/65 OUTLINE DIMENSIONS 1.05 1.00 0.80 0.15 0.05 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 0.65 BSC 0.20 1.20 0.09 MAX 8° 0.15 0.30 0° SEATING 0.05 0.19 COPLANARITY PLANE 0.10 COMPLIANT TO ...

Page 33

... Preliminary Technical Data ORDERING GUIDE Model Temperature Range AD5065BRUZ-1 1 −40°C to +105°C AD5065BRUZ-1REEL7 1 −40°C to +105°C AD5045BRUZ 1 −40°C to +105°C AD5045BRUZ-REEL7 1 −40°C to +105°C AD5025BRUZ 1 −40°C to +105°C 1 AD5025BRUZ-REEL7 −40°C to +105°C Eval-AD5065 EBZ 1 1 Eval-AD5045 EBZ ...

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