ir3500 International Rectifier Corp., ir3500 Datasheet
ir3500
Available stocks
Related parts for ir3500
ir3500 Summary of contents
Page 1
... DESCRIPTION The IR3500 Control IC combined with an xPHASE3 implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a multiphase converter. The XPhase3 expensive, and easier to design while providing higher efficiency than conventional approaches. ...
Page 2
... ORDERING INFORMATION Device IR3500MTRPBF * IR3500MPBF *Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. ...
Page 3
... Relative to VIDSEL Threshold between VR11 with/out Boot Voltage I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT 50.0 K OSC R = 24.5 K OSC R = 7.75 K OSC I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT Compare to V(VCCL) IR3500 ≤ 50.0 K OSC = 0.1µF +/-10%. SS/DEL MIN TYP MAX UNIT -0.5 0 ...
Page 4
... V(VCCL)=7V Error Amplifier Input Offset Voltage Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current R DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current Page TEST CONDITION To reach 1.1V = 24.5 K OSC IR3500 MIN TYP MAX UNIT 1.0 2.9 3.5 ms 0.8 2.2 3.25 ms 0.3 1.2 3.0 ms 0.5 1.2 2.3 ms ...
Page 5
... Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure V(VCCL)- V(ROSC/OVP) Page TEST CONDITION = 24.5 K OSC IR3500 MIN TYP MAX UNIT 120 250 mV 500 780 950 mV 125 ...
Page 6
... V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN) ≤ 3.3V Note 1 Note 1 I(VRRDY) = 4mA V(VRRDY) = 5.5V V(VO) < [V(VOSEN+) – V(LGND Compare to V(VCCL) V(VO) = 100mV I(VRHOT) = 30mA V(VRHOT) = 5.5V Compare to V(VCCL) Compare to V(VCCL) Compare to V(VCCL) IR3500 MIN TYP MAX UNIT - 0.2 0.4 0.6 mA ...
Page 7
... ROSC BUFFER AMPLIFIER 0. REMOTE SENSE AMPLIFIER + - ERROR AMPLIFIER + - IOCSET IVSETPT IROSC IROSC ROSC BUFFER AMPLIFIER 0. REMOTE SENSE AMPLIFIER + - IR3500 EAOUT 1k FB VSETPT RVDAC VDAC OCSET ROCSET CVDAC LGND ROSC ROSC VO EAOUT SYSTEM SET POINT VOSEN+ VOLTAGE VOSNS- VOSEN- EAOUT 1k FB VSETPT RVSETPT ...
Page 8
... VCCL Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. 29 VCCLFB Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. Page PIN DESCRIPTION June 12, 2007 IR3500 ...
Page 9
... PWM LATCH ENABLE + VID6 BODY - BRAKING RAMP COMPARATOR DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER + ISHARE VID6 - VID6 - 3K + VID6 VID6 DACIN Figure 4 - PWM Block Diagram IR3500 VCC VCCH GATEH CBST VCCL GATEL PGND CURRENT SENSE CSIN+ AMPLIFIER + CCS RCS - + + CSIN- VCC ...
Page 10
... It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of Page Figure 5 - Four Phase Oscillator Waveforms IR3500 June 12, 2007 ...
Page 11
... DUTY CYCLE DECREASE DUTY CYCLE DECREASE DUE TO LOAD DUE TO VIN INCREASE DECREASE (BODY BRAKING) OR FAULT (FEED-FORWARD) (VCC UV, OCP, VID FAULT) Figure 6 - PWM Operating Waveforms − MAX MIN = T SLEW V O − MAX MIN T = SLEW + BODYDIODE IR3500 STEADY-STATE OPERATION June 12, 2007 ...
Page 12
... Current Sense Amp CSOUT resistor connected to the ISHARE pin. The ISHARE pins of all the phases are IR3500 + the two time constants match, the June 12, 2007 ...
Page 13
... IR3500 THEORY OF OPERATION Block Diagram The Block diagram of the IR3500 is shown in Figure 8, and specific features are discussed in the following sections. VID Control The AMD 6-bit VID, VR11 8-bit VID, and AMD Opteron 5-bit VID are shown in Tables respectively, and are selected by different connections of VIDSEL pin shown in Table 1 ...
Page 14
ENABLE VBIAS VCCL COMPARATOR ENABLE 250nS - BLANKING + INTEL DELAY 850mV AMD 1.2V COMPARATOR 800mV 1.14V + VCCLDRV - 80mV VCCL REGULATOR 120mV AMPLIFIER DISCHARGE VCCLFB + 4.0V COMPARATOR - - 0.94 1.19V + VCCL OUTPUT 0.86 0.2V COMPARATOR ...
Page 15
... IR3500 Ignore VID Fault VID Fault Latch YES YES NO NO VID3 VID2 VID1 VID0 Vout( 0.7625 0.7500 ...
Page 16
... IR3500 Dec (VID7:VID0) Voltage 01000000 1.21250 01000001 1.20625 01000010 1.20000 01000011 1.19375 01000100 1.18750 01000101 1.18125 01000110 1.17500 01000111 1.16875 01001000 1.16250 01001001 1.15625 01001010 1.15000 01001011 1.14375 01001100 1 ...
Page 17
... EA 0.54375 EB 0.53750 EC 0.53125 ED 0.52500 EE 0.51875 EF 0.51250 F0 0.50625 F1 0.50000 F2 n/a F3 n/a F4 n/a F5 n/a F6 n/a F7 n/a F8 n/a F9 n/a FA n/a FB n/a FC n/a FD n/a FE n/a FF IR3500 Dec (VID7:VID0) Voltage 11000000 n/a 11000001 n/a 11000010 n/a 11000011 n/a 11000100 n/a 11000101 n/a 11000110 n/a 11000111 n/a 11001000 n/a 11001001 n/a 11001010 n/a 11001011 n/a 11001100 n/a 11001101 n/a 11001110 n/a 11001111 n/a 11010000 n/a 11010001 n/a 11010010 n/a 11010011 n/a 11010100 ...
Page 18
... IR3500 Voltage (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 ...
Page 19
... Start-up Sequence The IR3500 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down slope of the voltage at the SS/DEL pin respectively ...
Page 20
... SS/DEL, pull down EAOUT voltage and drive VRRDY low. However, the latches can only be reset by cycling VCCL power. Page VID SOFT START VID SAMPLE VRRDY DELAY TIME (TD2) TIME (TD3) TIME (TD4+TD5) TD4 TD5 IR3500 NORMAL OPERATION June 12, 2007 ...
Page 21
... The SS/DEL capacitor will discharge until it reaches 200 mV and the fault latch is reset allowing a normal soft start to occur over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. Page SOFT START VRRDY DELAY TIME (TD3) TIME (TD2) IR3500 NORMAL OPERATION June 12, 2007 ...
Page 22
... Figure 13 - Over Current Protection waveforms during and after soft start Linear Regulator Output (VCCL) The IR3500 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the resistor divider at VCCLFB pin ...
Page 23
... The over-voltage protection comparator monitors Vo pin voltage pin voltage exceeds VDAC by 130mV, as shown in Figure 14, IR3500 raises ROSC/OVP pin voltage to V(VCCL) - 1V, which sends over voltage signal to system. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit, which pulls the converter input low in over voltage conditions ...
Page 24
... IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain on until ISHARE pin voltage drops below V(VCCL) - 800mV, which signals the end of over voltage condition. An over voltage fault condition is latched in the IR3500 and can only be cleared by cycling power to the IR3500 VCCL. ...
Page 25
... VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ROSC/OVP 1.6V Figure 16 - Over-voltage protection during power-up 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 17 - Over-voltage protection with pre-charging converter output Vo > 1.73V Page 12V June 12, 2007 IR3500 ...
Page 26
... Open Remote Sense Line Protection The IR3500 checks for open remote sense lines every time it is enabled and will not power on if there is an open sense line fault. If either remote sense line VOSEN+ or VOSEN- or both are open, the output of the remote sense amplifier (VO) drops ...
Page 27
... PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault is registered. Phase Number Determination After a daisy chain pulse is started, the IR3500 checks the timing of the input pulse at PHSIN pin to determine the phase number. This information is used to have symmetrical phase delay between phase switching without the need of any external component. ...
Page 28
... VID1 IIN 8 17 VID0 RDRP1 VID0 VDRP RDRP ENABLE VRHOT RFB RCP RHOTSET2 RFB1 CFB RFB2 RHOTSET1 Figure 20 - IR3500 / IR3505 Three Phase AMD Opteron Converter Page FUSE ROVP1 Q3 SCR Q2 U10 ROVP2 1 ISHARE IR3505 2 DACIN PHASE 3 LGND IC 4 PHSIN CVDAC ...
Page 29
... VID0 8 17 CDRP RDRP1 VID0 VDRP RDRP ENABLE VRHOT RFB RCP CCP RHOTSET2 RFB1 CFB CCP1 RFB2 RHOTSET1 Figure 21 - IR3500 / IR3505 Six Phase VRM11.0 / VRD11.0 / EVRD11.0 Converter Page FUSE CVCC1 Q3 SCR U10 ROVP2 1 12 ISHARE SW IR3505 2 11 DACIN GATEH PHASE 3 ...
Page 30
... C / DEL SS / DEL − CHG after which the error amplifier output is released to allow , − CHG = IR3500 according to the OSC (1) The VID sample . (2) ( (4) − ( − (6) − (7) June 12, 2007 VR . ...
Page 31
... LIMIT sw =Ratio of the peak to average current for the inductor Determined by the ROSC and given by Figure 24, OCSET IR3500 ( fixed and can be quantified as OCDEL (10) as defined in VDAC (11) (12) and room temperature L_MAX − (13) ROOM (14) ∗ ...
Page 32
... VCCL (min) < VCCLDRV ( max) is the minimum and maximum anticipated input voltage. If the I HOTSET1 is calculated from (22). MAX IR3500 which is the O_NLOFST, is determined by (17), where VSETPT (17) (18) (19) (20) (21) or Darlington configuration can min and R HOTSET2 , the NTC THERM ...
Page 33
... MAX CS ∗ CCP1 RFB VO+ CCP RFB1 CFB - RDRP VDRP EAOUT EAOUT CDRP + (b) Type III compensation CP IR3500 )] (22 (23) is the required output impedance of O (25) and C removed. DRP DRP CCP1 RCP CCP FB - EAOUT EAOUT VDAC + and C from (26) and (27), where L CP June 12, 2007 ...
Page 34
... ∗ and C from (33) and (34 ∗ ∗ ∗ are not needed. Choose the crossover frequency fc between 1/10 and 1 IR3500 (26) (27) (28) (29) according to (30), and determine C (30) (31) (32) (33) (34) (35) June 12, 2007 and FB ...
Page 35
... Switching Frequency: f =250 kHz SW Output Inductors: L=470 nH Output Capacitors: Polymer, C=560uF, R IR3500 EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, R frequency of 250kHz per phase, choose R 11.9 uA. Soft Start Capacitor C SS/DEL Determine the soft start capacitor from the required soft start time. ...
Page 36
... TOFST CS OCSET − 3 − ∗ IR3500 − 6 ∗ ( 100 − Ω 11.9uA with OCSET . CS ⋅ ( − 108 ) 082 ⋅ − 108 ...
Page 37
... EXP [ 3520 T MAX _ ROOM − VCCL . − ( 142 931 * ) and C . DRP CP CP IR3500 DRP =20k , and calculate R VCCLFB2. (19) (20) (21) and R HOTSET2 =3520, and the NTC thermistor THERM 1 1 − = Ω 142 + + 273 115 273 Ω ...
Page 38
... SW Output Inductors: L=100 nH Output Capacitors: Ceramic, C=22uF, R IR3500 EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, R switching frequency of 800kHz per phase, choose R Soft Start Capacitor C SS/DEL Determine the soft start capacitor to meet the specifications of the delay time. ...
Page 39
... Resistor R VDAC VDAC 18 nF − Ω − − 3 − = ∗ 3850 * L _ MAX ROOM IR3500 mS − 6 ∗ − = Ω 100 40uA with OCSET . CS June 12, 2007 ...
Page 40
... < Ω 660 HOTSET1 is, MAX 1 3 − EXP [ 3520 ( * T 273 _ ROOM IR3500 ⋅ − 108 ) 126 ⋅ − 108 ) DRP =20k , and calculate R VCCLFB2. mA (19) (20) (21) and R HOTSET2 =3520, and the NTC thermistor ...
Page 41
... ∗ IR3500 , choose R =3.65k . Ω HOTSET1 =6.65k . DRP = 165 kHz − =2.2nF. DRP − ∗ ∗ Ω ...
Page 42
... Figure 23 - Frequency variation with ROSC. Figure 24 - ISETPT, OCSET with ROSC. Page IR3500 June 12, 2007 ...
Page 43
... Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes. • Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation components. Page and C OCSET VDAC VDAC SS/DEL IR3500 . Avoid using any via for the connection. June 12, 2007 ...
Page 44
... Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. Page IR3500 June 12, 2007 ...
Page 45
... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented or plugged from bottom board side with solder resist. Page IR3500 June 12, 2007 ...
Page 46
... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page IR3500 June 12, 2007 ...
Page 47
... C/W, θ JA Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information. www.irf.com IR3500 o = 0.86 C/W JC TAC Fax: (310) 252-7903 ...