ir3092 International Rectifier Corp., ir3092 Datasheet
ir3092
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ir3092 Summary of contents
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... AMD Opteron, 2) AMD Athlon or 3) Intel VR10.X family of processors. The user can select the appropriate VID range with a single pin. PWM Control and 2 phase gate drive functions are integrated into a single IC. In addition to CPU power, the IR3092 offers a compact, efficient solution for high current POL converters. ...
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... Output that drives high during an Over-Voltage condition. 42 ENABLE Enable Input. A logic low applied to this pin puts the IC into Fault mode. 43-44 N/C No Connect. 45 VID5 Inputs to VID Converter 46 VID0 Inputs to VID Converter 47 VID1 Inputs to VID Converter 48 VID2 Inputs to VID Converter Page IR3092 06/25/04 ...
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... DC -0.3V 3A for 100ns, 200mA DC -0.3V DC, -2V for 100ns 3A for 100ns, 200mA DC -0.3V n/a n/a n/a -0.3V 250mA -0.3V 250mA -0.3V 1mA -0.3V 1mA n/a n/a n/a n/a -0.3V 1mA -0.3V 1mA -0.3V 1mA -0.3V 1mA IR3092 ISINK 1mA 1mA 1mA 10mA 1mA 1mA 5mA 1mA 20mA 1mA 5mA n/a 1mA 1mA 250mA n/a n/a 1mA 20mA 1mA n/a 1mA n/a n/a n/a n/a n/a ...
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... TYP MAX 0 0.4 0.6 0.8 1.3 1.5 1.7 1.0 1.2 1.4 3.0 3.4 3.8 2.1 2.6 3 100 60 190 375 4.5 4.9 5.2 0.5 1 100 105 4 7 1.25 280 380 500 .75 1.0 1.5 4.5 4.9 5.3 90 150 -125 0 125 0.2 3. 200 280 400 06/25/04 IR3092 UNIT % MHz V/ ...
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... Enable Input Threshold, INTEL VID_SEL=0, Referenced to VOSNS- Threshold, AMD VID_SEL=Float, Referenced to VOSNS- Input Resistance Pull-up Voltage Page TEST CONDITION = 42k ROSC = 42k ROSC = 42k ROSC IR3092 MIN TYP MAX UNIT 160 200 240 kHz 155 170 190 ° PA 105 115 125 0 ...
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... Note1 Offset Voltage Mismatch Monitor I(SCOMP) o Gain Gain 125 C J Gain Mismatch Differential Input Range Common Mode Input Range Page TEST CONDITION . IR3092 MIN TYP MAX UNIT 0.5V ...
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... Compare V(FB) to V(VDAC) VID_SEL=0V. Compare to V(VDAC) Float VID_SEL. Compare to V(VDAC) VCCL = 12V. V(EAOUT)=0V. Step FB 460mV above V(VDAC). Measure time to GATELX transition to >1V. OVP to PGND1 I(OVP)=10mA, V(VCC)-V(OVP) -0.3V VOSNS- 0.3V, All VID Codes IR3092 MIN TYP MAX UNIT - 1 %/% ...
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... Peak Gate Drive Current vs. Load Capacitance 4.0 3.5 3.0 Frequency 2.5 FB Bias OCSET Bias 2.0 SETBIAS 1.5 1 100 1 I(VDAC) Sink and Source Currents vs. ROSC I(VDAC) Source Current I(VDAC) Sink Current ROSC in Kohms I(SETBIAS) vs. ROSC ROSC in Kohms I(RISE) I(FALL) c 3.5 6 8.5 11 13.5 16 C(GATEX 06/25/04 IR3092 90 100 90 100 18.5 21 ...
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... TYPICAL OPERATING CHARACTERISTICS Error Amplifier Frequency Response 100 0 93dB DC gain 88° Phase Margin 3.1MHz Crossover -100 -180 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz DB(V(comp)) P(V(comp)) Frequency Page 10MHz 100MHz 1.0MHz IR3092 06/25/04 ...
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... VID3 PWM Operation The IR3092 is a fully integrated 2 phase interleaved PWM control IC which uses voltage mode control with trailing edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the control IC is used for the voltage control loop. The PWM block diagram of the IR3092 is shown in Figure 2. ...
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... RESET DOMINANT IROSC Share Adjust Error Amp + 10p 0. IROSC*3/4 - VDAC X24.5 VDAC X24.5 Figure 2 – PWM Block Diagram VIN GATEH1 1 2 GATEL1 RCS1 CCS1 VIN GATEH2 1 2 GATEL2 RCS2 CCS2 - CSINP2 + CSINM - CSINP1 + 06/25/04 IR3092 VOUT SENSE+ VOUT+ COUT VOUT- VOUT SENSE- ...
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... V SLEW MAX MIN RAMP2 MIN DUTY RAMP2 MAX DUTY CYCLE ADJUST CYCLE ADJUST THE SHARE ADJUST ERROR AMPLIFIER CAN CHANGE THE PULSE WIDTH OF RAMP2 FROM 0.5x RAMP1 TO 2.0x RAMP1 TO FORCE CURRENT SHARING Vout . The minimum time BODY DIODE ) BODY DIODE 06/25/04 IR3092 ...
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... This reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the IR3092 IC junction is hotter than the inductors these two effects tend to cancel such that no additional temperature compensation of the load line is required. ...
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... Disable Comparator has been included to prevent false OVP firing during dynamic VID down changes. The BB DISABLE Comparator disables Body Braking then be controlled to keep V(FB) and V(VOUT) within 80mV of V(VDAC), below the 150mV INTEL OVP trip point. Page when FB exceeds VDAC by 80mV. The low side MOSFETs will IR3092 06/25/04 ...
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... This trim method provides 0.5% system accuracy. ROSC The IR3092 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The IR3092 detects a VID change and blanks the DAC output response for 400ns to verify the new code is valid and not due to skew or noise ...
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... DAC 2 C DAC I SOURCE DAC IR3092 TO FAULT VID=11111X FAULT BLANKING, 3.3us "SLOW" VDAC DAC BUFFER - "FAST" VDAC + IROSC and their value can be found using the ROSC, can be programmed by the DOWN is used to compensate VDAC DAC is proportional to the down-slope slew ...
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... OFF 1 1 IR3092 Vout VID2 VID1 VID0 ( 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 ...
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... I(SETBIAS) vs. Rosc curve in the Typical Operating Characteristics Section. Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3092 has a programmable soft-start function to limit the surge current during converter power-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing as well as over-current protection delay and hiccup mode timing ...
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... VOUT PWRGD IOUT START-UP NORMAL OPERATION (5VUVL GATES (VOUT CHANGES DUE TO FAULT MODE) LOAD AND VID CHANGES) Page OCP THRESHOLD OCP HICCUP OVER-CURRENT DELAY PROTECTION Figure 8 – Operating Waveforms IR3092 7.6V UVLO RE-START POWER-DOWN AFTER OCP (VCC GATES CLEARS FAULT MODE) 06/25/04 ...
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... Typical Operating Characteristics. ROSC Vin Vo ) LIMIT ( ) Vin * fsw t SS (4) t OCDEL ( the required over current limit. I LIMIT (8) OCSET 06/25/04 IR3092 and the delay time the OCSET, ...
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... The offset and slope of the converter output impedance are independent DRP. VDAC VDAC ERROR AMPLIFIER + VOSNS IROSC EAOUT VDRP BUFFER + VDRP - - VOUT SENSE+ VOUT SENSE- Figure 9 - Adaptive voltage positioning IR3092 which forces the FB VDAC CSINM3 X24.5 - CSINP3 + VDAC CSINM2 X24.5 - CSINP2 + 06/25/04 , ROSC is ...
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... NLOFST ROSC DRP O_NLOFST , pumps current I ROSC * (9) (10 and capacitor C CS 06/25/04 IR3092 which is the out of the ROSC where R is the O is the ...
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... CSO I CSIN ¦ CSO CS I CSIN ¥ VDAC VDAC ERROR AMPLIFIER + VOSNS IROSC VDRP BUFFER RDRP + VDRP - VOUT SENSE+ RFB RLINEAR RNTC IR3092 and calculate (12) should be less than 2 CS EAOUT Current + VDAC 06/25/04 as follows. CS, ...
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... RFB1 - VDRP EAOUT EAOUT + (b) Type III compensation Figure11 . Voltage loop compensation network are the equivalent capacitance and ESR of output capacitors respectively and DRP CCP1 RFB RCOMP CCOMP CFB FB - EAOUT EAOUT VDAC RDRP + CDRP (13) 06/25/04 IR3092 is LE ...
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... (19) DRP and C from Equations (20) and (21), where F COMP COMP COMP COMP R COMP (14) (15) is the input voltage (16) according to Equation (17), FB1 R FB (20) (21) 06/25/04 IR3092 is the PWM M is the PWM M ...
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... BIASOUT pin provides 150mA open-looped regulated voltage for GATE drive bias, and the voltage is set by SETBIAS through an external resistor Rset connecting between SETBIAS pin and ground. Bias current I ROSC. Rset is chosen by equation (23) Page RAMP V BIASOUT R SET I SETBIAS IR3092 (22 function of SETBIAS (23) 06/25/04 ...
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... Output Capacitors: C =0.011F External Components of IR3092 Oscillator Resistor Rosc Once the switching frequency is chosen, R IR3092 data sheet. For switching frequency of 180 kHz per phase, Choose R =47.5k OSC Soft Start Capacitor C SS Calculate the soft start capacitor from the required soft start time 6mS. ...
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... The power good delay time VccPG I CHG VDAC Slew Rate Programming Capacitor C From IR3092 data sheet, the sink current I Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. SINK C VDAC ...
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... 450 011 ! need to get desired dynamic load response performance. COMP Choose R = 9.53k DRP CSO Choose R = CSO =82.5k SET and C . COMP : 011 * 175 nF 06/25/04 IR3092 17 kHz ...
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... Vcc Vbias ) Pdrv Preg Pdiss T ˜ Icq ˜ Iqh ( ˜ Iql ( " Pq 0.588 ( ) W º ¼ ˜ ˜ Qgs ) 10 Pdrv term in the equation gives the total average Preg 0.158 ( ) W Pdiss 1. 27.281 06/25/04 IR3092 0.264 ( ) W ...
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... Figure 13. 12V Control, 5V Power, VR10.0 Converter Page 12VIN GATEH1 PGND1 GATEL1 VCCL 12VIN 5VUVL GATEL2 PGND2 GATEH2 VCCH2 5VIN 12VIN GATEH1 PGND1 GATEL1 VCCL 5VUVL GATEL2 PGND2 GATEH2 VCCH2 5VIN IR3092 VCORE VRETURN 1 2 5VIN 1 2 VCORE VRETURN 06/25/04 ...
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... Route the high current paths using wide and short traces or polygons. Use multiple vias for connections between layers. x The symmetry of the following connections from phase to phase is important for proper operation: - The Kelvin connections of the current sense signals to inductors. - The gate drive signals from the IC to the MOSFETS. - The polygon shape of switching nodes. Page IR3092 06/25/04 ...
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... The maximum length and width of the center land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page IR3092 06/25/04 ...
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... Figure 14. PCB metal and solder resist. Page IR3092 06/25/04 ...
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... Figure 15. PCB metal and component placement. Page IR3092 06/25/04 ...
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... Page Figure 16. Stencil design. IR3092 06/25/04 ...
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... Page Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information IR3092 TAC Fax: (310) 252-7903 www.irf.com 06/25/04 ...