ir3093m International Rectifier Corp., ir3093m Datasheet

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... OVP Flag Output detects high side fet short at powerup x Pin compatible with IR3092, 2-phase PWM Control IC x Available 48L MLPQ package ORDERING INFORMATION Device IR3093MTR *IR3093M * Samples Only PACKAGE INFORMATION Page PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC VID3 GATEH1 VID4 ...

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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 VID3 Inputs to VID Converter 2 VID4 Inputs to VID Converter 3 ROSC Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, ...

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ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 PIN NAME VMAX 1 VID3 30V 2 VID4 30V 3 ROSC 30V 4 VOSNS- 0.5V 5 OCSET 30V 6 VDAC 30V 7 VDRP 30V 8 FB 30V 9 EAOUT 10V 10 ...

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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 7. 28V, C =3.3nF, C CCHX GATEHX PARAMETER VDAC Reference System Set-Point Accuracy Sink Current Source Current VID Input Threshold, INTEL VID Input Threshold, AMD VID_SEL OPTERON Threshold VID_SEL ...

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PARAMETER VDRP Buffer Amplifier cont. Source Current Sink Current Oscillator Switching Frequency R Phase Shift Sequence: GATEH1-GATEH2-GATEH3 BIASOUT Regulator SETBIAS Bias Current R Set Point Accuracy V(SETBIAS)-V(BIASOUT) @ 100mA BIASOUT Dropout Voltage I(BIASOUT)=100mA,Threshold when V(SETBIAS)-V(BIASOUT)=0.45V BIASOUT Current Limit Soft Start ...

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PARAMETER PWRGD Output Output Voltage I(PWRGD) = 4mA Leakage Current V(PWRGD) = 5.5V Enable Input Threshold, INTEL VID_SEL=0, Referenced to VOSNS- Threshold, AMD VID_SEL=Float, Referenced to VOSNS- Input Resistance Pull-up Voltage Gate Drivers GATEH Rise Time VCCHX = 8V, Measure ...

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PARAMETER Share Adjust Error Amplifier Input Offset Voltage MAX Duty Cycle Adjust Ratio MIN Duty Cycle Adjust Ratio Transconductance SCOMPX Source/Sink Current Equal Duty Cycle Comparator Threshold Duty Cycle Match at Startup SCOMPX Precharge Current 0% Duty Cycle Comparator Threshold ...

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TYPICAL OPERATING CHARACTERISTICS I(VDAC) Sink and Source Currents vs. ROSC 180 160 140 120 100 ROSC in Kohms Oscillator freq vs. ROSC 500 450 400 350 300 250 ...

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Peak Low side Gate drive current vs. Laod capacitance 3.250 3.000 2.750 2.500 2.250 2.000 1.750 1.500 1.250 1.000 C(GATELX Error Amplifier Frequency Response 180 100 0 93dB DC gain 88° Phase Margin ...

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VCC 5VREF ROSC FB LGND INTERNAL IROSC UVL REFERENCE - 4 X IROSC + SETBIAS 7.9V START 1.243 7.4V STOP BIASOUT IROSC UVL 5VUVL - CLK1 + 4.36V START CLK2 4.17V STOP CLK3 PWRGD Oscillator OVER CURRENT OCSET - IAVE ...

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PWM Operation The IR3093 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage control ...

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INTERNAL OSCILLATOR RAMP DUTY CYCLE CLK1 CLK2 CLK3 EAOUT 0.6V RAMP1 SLOPE = 50mV / % DC The RSFF is reset dominant allowing both phases zero duty cycle within a few tens of nanoseconds in response ...

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Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased more. This patent pending technique is referred to as “body braking” and is accomplished through ...

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VCC Under Voltage Lockout (UVLO) The VCC UVLO function monitors the IR3093’s VCC supply pin and ensures enough voltage is available to power the internal circuitry. During power-up the fault latch is reset when VCC exceeds 7.9V and all other ...

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TM A Body Braking Disable Comparator has been included to prevent false OVP firing during dynamic VID down changes. The BB DISABLE Comparator disables Body Braking MOSFETs will then be controlled to keep V(FB) and V(VOUT) within 80mV of V(VDAC), ...

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APPLICATIONS INFORMATION VIN CIN GNDIN ENABLE OVP VID5 VID0 VID1 VID2 VID3 U13 VID4 RROSC CDAC VID3 VID4 ROSC RFB RDAC ROCSET VOSNS- OCSET RDRP VDAC VDRP FB EAOUT CCOMP RCOMP SS/DEL SCOMP2 SCOMP3 CSC2 CSC3 CSS Csense- RSC2 RSC3 ...

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VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. 18uA ...

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AMD Opteron VID Table VID_SEL Open. V(VDAC) is pre- positioned 50mV higher than Vout values listed below for load positioning. Vout is measured at EAOUT with ROSC=47K and a 1890 ohm resistor connecting FB to EAOUT to cancel the 50mV ...

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INTEL VR-10.0 VID Table (VID_SEL Grounded, measured at EAOUT=FB. ) Processor Pins (0 = low high) VID4 VID3 VID2 VID1 ...

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Oscillator Resistor R ROSC The oscillator frequency is programmable from 100kHz to 540kHz with an external resistor R Figure 6 oscillator generates an internal 50% duty cycle sawtooth signal (Figure 3.) that is used to generate 120° out-of-phase timing pulses ...

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VCC (12V) 4.36V 5VUVL 3.75V SS/DEL 1.1V VOUT PWRGD IOUT START-UP NORMAL OPERATION (5VUVL GATES (VOUT CHANGES DUE TO FAULT MODE) LOAD AND VID CHANGES) t Soft-start delay time is the time SS/DEL charged up to 1.1V. After that the ...

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A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions over- current fault occurs ...

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AMD specifies the acceptable power supply regulation window as 50mV around their specified VID tables. VR- 10.0 specifies the VID table voltages as the absolute maximum power supply voltage. In order to have all three DAC options, the OPTERON and ...

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Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor. The equation of the sensing network is, Usually the ...

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Figure 10 - Temperature compensation of inductor DCR Remote Voltage Sensing To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects directly to the load. The VDAC voltage is referenced to VOSNS- ...

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Compensation of the Current Share Loop The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. A 22nF capacitor ...

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R COMP optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. CP1 A ceramic capacitor between 10pF and 220pF is usually enough. In equation (17), V the PWM ...

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DESIGN EXAMPLE IR3093 Demo Board for VRD10.1 Application Specifications: Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =101 Output Current Limit set point: I ...

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The power good delay time ¨ VccPG I CHG VDAC Slew Rate Programming Capacitor C From IR3093 data sheet, the sink current I Calculate the VDAC down-slope ...

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NLOFST MAX CS _ MIN R DRP Choose R = 3.09k ...

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MathCAD file to estimate the power dissipation of the IC this Mathcad file step by step shows how to estimate the power dissipation of IR3093 . Initial Conditions:  No.of Phases Supply Voltage: Vcc Total High side Driver ...

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APPLICATION CIRCUIT - 3 PHASE OPTERON CONVERTER Figure 12. 12V Control, 12V Power Opteron Converter Page VCCH1 GATEL3 VCCL3 NC CSINM1 VID_SEL CSINP1 CSINM2 OVP CSINP2 ENABLE PWRGD OVPSNS BIASOUT 5VREF CSINM3 VID5 CSINP3 VID0 VCC VID1 ...

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APPLICATION CIRCUIT - 3 PHASE VR10.X CONVERTER Figure 13. 12V Control, 5V Power, VR10 Converter Page VCCH1 GATEL3 VCCL3 NC CSINM1 VID_SEL CSINP1 CSINM2 OVP CSINP2 ENABLE PWRGD OVPSNS BIASOUT 5VREF CSINM3 VID5 CSINP3 VID0 VCC VID1 ...

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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6 – System Diagram. x Dedicate at ...

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PCB AND STENCIL DESIGN METHODOLOGY x 7x7 x 48 Lead x 0.5mm pitch MLPQ See Figures 14-16. PCB Metal Design (0.5mm Pitch Leads) 1. Lead land width should be equal to nominal part lead width. The minimum lead to lead ...

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Figure 14. PCB metal and solder resist. Page IR3093 07/15/04 ...

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Figure 15. PCB metal and component placement. Page IR3093 07/15/04 ...

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Page Figure 16. Stencil design. IR3093 07/15/04 ...

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PACKAGE DIMENSIONS IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification ...