ltc1407a-1 Linear Technology Corporation, ltc1407a-1 Datasheet
ltc1407a-1
Related parts for ltc1407a-1
ltc1407a-1 Summary of contents
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... MS package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low power and tiny package makes the LTC1407-1/LTC1407A-1 suitable for high speed, portable applications. The LTC1407-1/LTC1407A-1 contain two separate differ- ential inputs that are sampled simultaneously on the rising edge of the CONV signal ...
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... V DD – GND MSE PACKAGE 10-LEAD PLASTIC MSOP = 125°C, θ 150°C/ W JMAX JA MSE PART MARKING LTBGT LTBGV LTBGW LTBGX http://www.linear.com/leadfree/ = 3V. LTC1407-1 LTC1407A-1 TYP MAX MIN TYP MAX UNITS 14 ±0.25 ±0.5 2 –4 4 ±1 ±2 10 –20 20 ±0.5 ±1 5 –10 10 ± ...
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... DD OUT V = 2.7V 1.6mA DD OUT OUT 0V OUT OUT DD LTC1407-1/LTC1407A /CH1 with = 1.5V DC. CM LTC1407-1 LTC1407A-1 MIN TYP MAX MIN TYP MAX 70.5 73.5 ● 68 70.5 70 73.5 72.0 76.3 72.0 76.3 –87 –90 ● –83 –77 – –82 –82 0. ...
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... Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period. Note 17: The LTC1407A-1 is measured and specified with 14-bit Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specified with 12-bit Resolution (1LSB = 610µV). ...
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... FREQUENCY (kHz) LTC1407-1/LTC1407A 3V 25°C. Single ended signals drive 1.5V DC (LTC1407A-1) CM SFDR vs Input Frequency 104 100 0 FREQUENCY (MHz) 14071 G02 THD, 2nd and 3rd vs Input ...
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... OUTPUT CODE 14071 G10 3V 1.5V DC (LTC1407A-1) CM 748kHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 185k ...
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... CH0 CH1 –50 –55 –60 CH0 AND CH1 –65 FALLING – 14071 G17 LTC1407-1/LTC1407A 3V 25°C. Single ended signals drive 1.5V DC (LTC1407A-1) CM SINAD vs Conversion Rate EXTERNAL V = 3.3V fS/3 REF IN 70 EXTERNAL V = 3.3V fS/40 REF ...
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... Two and pulses with SCK in fixed high or fixed low state starts Nap mode. Four or more pulses with SCK in fixed high or fixed low state starts Sleep mode 3V 25°C (LTC1407-1/LTC1407A- Reference Voltage vs Load Current 0 0.2 0.4 ...
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... S & H – CH0 – CH1 4 S & H – – CH1 5 V REF 3 10µF GND 6 11 EXPOSED PAD LTC1407-1/LTC1407A-1 10µ 3Msps MUX 14-BIT ADC 2.5V REFERENCE LTC1407A-1 THREE- STATE SDO SERIAL 8 OUTPUT PORT 10 CONV TIMING LOGIC SCK 9 1407A1 BD 14071fa 9 ...
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... LTC1407-1/LTC1407A DIAGRA S 10 14071fa ...
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... SLEEP V REF NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK SDO Nap Mode Waveforms t 1 Sleep Mode Waveforms t 1 SCK to SDO Delay SCK SDO V OL LTC1407-1/LTC1407A 1407 TD02 90% 10% 14071 TD03 14071fa 11 ...
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... U U APPLICATIO S I FOR ATIO DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1407-1/ LTC1407A-1 are easy to drive. The inputs may be driven differentially single-ended input (i.e., the CH0 input is AC grounded at V /2). All four analog inputs of CC both differential analog input pairs, CH0 + – ...
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... INPUT RANGE The analog inputs of the LTC1407-1/LTC1407A-1 may be driven fully differentially with a single supply. Either input may swing up to 3V, provided the differential swing is no greater than 1.25V. In the valid input range, each input of each channel is always up to ± ...
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... LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is 2’s complement with 1LSB = 2.5V/16384 = 153µV for the LTC1407A-1 and 1LSB = 2.5V/4096 = 610µV for the REF LTC1407-1. The LTC1407A-1 has 1LSB RMS of Gaussian white noise. Figure 6a shows the LTC1819 converting a ...
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... U2 1/2 LT1819 + Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially Board Layout and Bypassing Wire wrap boards are not recommended for high resolu- tion and/or high speed A/D converters. To obtain the best performance from the LTC1407-1/LTC1407A-1, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible ...
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... LTC1407-1/LTC1407A-1 Pin 6 to the power supply should be low impedance for noise-free operation. The Exposed Pad of the 10-lead MSE package is also tied to Pin 6 and the LTC1407-1/LTC1407A-1 GND. The Exposed Pad should be soldered on the PC board to reduce ground connection inductance. Digital circuitry grounds must be connected to the digital supply common ...
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... BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1407-1/ LTC1407A-1 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1407-1/ LTC1407A-1. This configuration is adequate to traverse a ...
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... LTC1407-1/LTC1407A APPLICATIO S I FOR ATIO ; 12-03-03 ****************************************************************** ; Files: 014SIAB.ASM -> 1407A Sine wave collection with Serial Port interface ; bvectors.asm both channels collected in sequence in the same 2k record. ; s2k14ini.asm Buffered mode 2k buffer size. ; First element at 1024, last element at 1023, two middles at 2047 and 0000 ...
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... BVECTORS.ASM ;initialize buffered serial port ;clear a chunk at the end to mark the end ;The vectors start here ;get BSP vectors ;Set address of BSP buffer for clearing ;Set address of result for clearing LTC1407-1/LTC1407A-1 10.Jul.96 * 14071fa 19 ...
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... LTC1407-1/LTC1407A APPLICATIO S I FOR ATIO .title “Vector Table” .mmregs reset goto #80h ;00; RESET nop nop nmi return_enable ;04; non-maskable external interrupt nop nop nop trap2 goto #88h ;08; trap2 nop nop .space 52*16 ;0C-3F: vectors for software interrupts 18-30 int0 return_enable ;40; external interrupt int0 ...
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... Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/ ~~~~~~~\_______/~~~~~* *C542 read 0 B13 B12 negative edge BCLKR * negative BFSR pulse * no data shifted * 1' cable from counter to CONV at DUT W U B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 LTC1407-1/LTC1407A 14071fa 21 ...
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... LTC1407-1/LTC1407A APPLICATIO S I FOR ATIO * 2' cable from counter to CLK at DUT *No right shift is needed to right justify the input data in the main program * *the two msbs should also be masked * ***************************************************************************************************** * Loopback .set NO Format .set BIT_16 IntSync .set NO IntCLK .set NO BurstMode .set YES CLKDIV ...
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... TYP 0.53 ± 0.152 (.021 ± .006) DETAIL “A” SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP LTC1407-1/LTC1407A-1 BOTTOM VIEW OF EXPOSED PAD OPTION 2.06 ± 0.102 (.081 ± .004) 1 1.83 ± 0.102 (.072 ± .004) 10 0.497 ± 0.076 (.0196 ± .003) ...
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... LTC1407-1/LTC1407A-1 RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC1608 16-Bit, 500ksps Parallel ADC LTC1609 16-Bit, 250ksps Serial ADC LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC LTC1411 14-Bit, 2.5Msps Parallel ADC LTC1420 ...