st62t62c STMicroelectronics, st62t62c Datasheet
st62t62c
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... ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port) DEVICE SUMMARY EPROM OTP DEVICE (Bytes) (Bytes) ST62T52C 1836 ST62T62C 1836 ST62E62C 1836 February 2002 ST62T62C/E62C (See end of Datasheet for Ordering Information) EEPROM - 64 64 ST62T52C PDIP16 PSO16 SSOP16 CDIP16W Rev. 3.0 1/78 ...
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... ST62T52C ST62T62C/E62C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.3 . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST6252C ST6262B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The ST62E62C is the erasable EPROM version of the ST62T62C device, which may be used to em- ulate the ST62T52C and ST62T62C devices as well as the ST6252C and ST6262B ROM devices. OTP and EPROM devices are functionally identi- cal ...
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... ST62T52C ST62T62C/E62C 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins ...
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... MEMORY 0FF0h INTERRUPT & RESET VECTORS 0FFFh ST62T52C ST62T62C/E62C Briefly, Program space contains user program code in OTP and user vectors; Data space con- tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. ...
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... ST62T52C ST62T62C/E62C MEMORY MAP (Cont’d) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register) ...
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... WATCHDOG REGISTER AR TIMER RELOAD/CAPTURE REGISTER AR TIMER COMPARE REGISTER AR TIMER LOAD REGISTER EEPROM RESERVED - bytes DATA RAM/EEPROM REGISTER RESERVED EEPROM CONTROL REGISTER RESERVED ACCUMULATOR * WRITE ONLY REGISTER ST62T52C ST62T62C/E62C 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h ...
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... ST62T52C ST62T62C/E62C MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- dress 0000h and 0FFFh (top memory address de- pends on the specific device) ...
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... E²PROM page (when available) when the parallel writing mode is set for the E²PROM, as defined in EECTL register. Table 3. Data RAM Bank Register Set-up DRBR 10h other ST62T52C ST62T62C/E62C ST62T52C ST62T62C None None Not available EEPROM page 0 Not Available Not Available Not available Not available ...
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... ST62T52C ST62T62C/E62C MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4 . EEPROM locations are accessed di- rectly by addressing these paged sections of data space ...
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... E2ENA and E2PAR2 bits are also set. Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set. ST62T52C ST62T62C/E62C EEPROM Control Register (EECTL) Address: EAh — Read/Write Reset status: 00h 7 E2O ...
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... PC menu (PC driven Mode) or automatically (stand-alone mode). 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T62C is described in the User Manual of the EPROM Programming Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from STMicroelectronics ...
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... EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEP- ROM data memory can be performed either through the application software or through an ex- ST62T52C ST62T62C/E62C ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem- ory ...
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... ST62T52C ST62T62C/E62C 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or ST62T52C ST62T62C/E62C a RETI instructions occurs. As the NMI mode is automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. ...
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... ST62T52C ST62T62C/E62C 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor ( addition, a Low Frequency Auxiliary Os- ...
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... OSG and it should not be ena- bled in applications that use the SPI or the UART. It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature). ST62T52C ST62T62C/E62C Figure , is limited to INT Figure 12.. ...
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... ST62T52C ST62T62C/E62C CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure 10. OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator Internal ...
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... When the OSG is enabled, access to this area is prevented. The internal frequency is kept When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is OSG Min. prevented. The internal frequency is kept at f ST62T52C ST62T62C/E62C POR Core : 13 TIMER 1 f Watchdog ...
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... ST62T52C ST62T62C/E62C 3.2 RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...
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... RESET 3.2.5 Application Notes No external resistor is required between V the Reset pin, thanks to the built-in pull-up device. ST62T52C ST62T62C/E62C ues, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply ...
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... ST62T52C ST62T62C/E62C RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the In- terrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode ...
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... FFh 0D2h 7Fh 0D8h FEh 0D1h 40h ST62T52C ST62T62C/E62C Comment EEPROM enabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled AR TIMER stopped As written if programmed Max count loaded A/D in Standby ...
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... ST62T52C ST62T62C/E62C 3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and ...
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... Figure 17. Watchdog Counter Control (DWDR Figure 17.. D7 ST62T52C ST62T62C/E62C C SR RESET OSC 12 VR02068A 27/78 ...
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... ST62T52C ST62T62C/E62C DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active) ...
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... STOP/WAIT modes. Figure 19. Digital Watchdog Block Diagram RESET Q RSFF R S DB0 Figure 18. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH SET DB1.7 LOAD SET 8 WRITE RESET DATA BUS ST62T52C ST62T62C/E62C NMI I/O VR02002 -12 OSCILLATOR CLOCK VA00010 29/78 ...
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... ST62T52C ST62T62C/E62C 3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated interrupt service routine. These vectors are located in Pro- ...
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... The interrupt is serviced. – Return from interrupt (RETI) ST62T52C ST62T62C/E62C MCU – Automatically the MCU switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous PC value from the stack ...
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... ST62T52C ST62T62C/E62C INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h — Write Only ...
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... IOR REG. C8H, bit 6 FF CLK Q CLR I Start 2 IOR REG. C8H, bit 5 OVF OVIE CPF CPIE EF EIE TMZ ETI EOC EAI FF CLK Q CLR I Start 0 Bit GEN (IOR Register) ST62T52C ST62T62C/E62C INT #1 (FF6,7) RESTART FROM STOP/WAIT INT #2 (FF4,5) INT #3 (FF2,3) INT #4 (FF0,1) NMI (FFC,D) VA0426K 33/78 ...
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... ST62T52C ST62T62C/E62C 3.5 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a “ ...
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... Nevertheless, two cases must be consid- ered: – If the interrupt is a normal one, the interrupt rou- tine in which the WAIT or STOP mode was en- ST62T52C ST62T62C/E62C tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode ...
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... ST62T52C ST62T62C/E62C 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with pull-up, but without interrupt – Analog input – ...
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... Mode Input With pull-up, no interrupt Input No pull-up, no interrupt Input With pull-up and with interrupt Input Analog input (when available) Output Open-drain output (20mA sink when available) Output Push-pull output (20mA sink when available) ST62T52C ST62T62C/E62C Option 37/78 ...
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... ST62T52C ST62T62C/E62C I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated in 23.. All other transitions are potentially risky and ...
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... Open drain output PC2-PC3 5mA Open drain output PB0, PB2-PB3,PB6-PB7 30mA PA4-PA5 Push-pull output PC2-PC3 5mA Push-pull output PB0, PB2-PB3,PB6-PB7 30mA Note 1. Provided the correct configuration has been selected. (1) SCHEMATIC ST62T52C ST62T62C/E62C Data in Interrupt Data in Interrupt Data in Interrupt ADC Data out Data out 39/78 ...
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... ST62T52C ST62T62C/E62C I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PW- MOE is high, ARTMout/PB7 is the PWM output, in- dependently of the port registers configuration. Figure 24. Peripheral Interface Configuration of AR Timer ...
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... PSC INT ST62T52C ST62T62C/E62C The prescaler input is the internal frequency (f divided by 12. The prescaler decrements on the 15 . rising edge. Depending on the division factor pro- grammed by PS2, PS1 and PS0 bits in the TSCR (see Table 13.), the clock input of the timer/coun- ter register is multiplexed to different sources ...
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... ST62T52C ST62T62C/E62C TIMER (Cont’d) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (f ÷ 12). INT The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR ...
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... Timer Counter Register (TCR) Address: 0D3h — Read/Write Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h — Read/Write Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits. ST62T52C ST62T62C/E62C PS1 PS0 Divided ...
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... ST62T52C ST62T62C/E62C 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ...
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... ARTIMin SL0-SL1 EF SYNCHRO DATA BUS 8 AR COMPARE REGISTER 8 CPF COMPARE 8 OVF 8-Bit LOAD AR COUNTER RELOAD/CAPTURE LOAD REGISTER REGISTER 8 8 DATA BUS ST62T52C ST62T62C/E62C DDRB7 DRB7 PB7/ ARTIMout R S PWMOE OVF OVIE TCLD EIE EF AR TIMER INTERRUPT CPF CPIE VR01660A 45/78 ...
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... ST62T52C ST62T62C/E62C AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ARCP register must be greater than the contents of the ARRC register. ...
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... ARTIMin pin). Load on External Input. The counter operates as a free running 8-bit counter fed by the prescaler. ST62T52C ST62T62C/E62C the count is incremented on every clock rising edge. Each counter overflow sets the ARTIMout pin. A ...
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... ST62T52C ST62T62C/E62C AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different operating modes of the AR Timer, to enable the clock and to initialize the counter ...
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... AR Compare Register. The CP compare register is used to hold the compare value for the compare function. AR Compare Register (ARCP) Address: DAh — Read/Write Bit 7-0 = D7-D0: Compare Data Bits . These are the Compare register data bits. Table ST62T52C ST62T62C/E62C ...
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... ST62T52C ST62T62C/E62C 4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of 70us (at an oscillator clock frequency of 8MHz). The ADC converts the input voltage by a process ...
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... A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode). Bit 3-0 = D3-D0. Not used A/D Converter Data Register (ADR) Address: 0D0h — Read only Bit 7-0 = D7- Bit A/D Conversion Result. ST62T52C ST62T62C/E62C 0 STA PDS ...
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... ST62T52C ST62T62C/E62C 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction ...
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... Data space register . Affected * . Not Affected ST62T52C ST62T62C/E62C Load & Store. These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. ...
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... ST62T52C ST62T62C/E62C INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space memory con- Table 17. Arithmetic & Logic Instructions ...
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... JP abc Extended Notes: abc. 12-bit address Not Affected ST62T52C ST62T62C/E62C Control Instructions. The control instructions control the MCU operations during program exe- cution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. ...
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... ST62T52C ST62T62C/E62C Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 CALL abc 0001 1 pcr 2 ext 1 2 JRNZ 4 CALL ...
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... Indicates Illegal Instructions Cycle 5 Bit Displacement Operand 3 Bit Address 1byte dataspace address Bytes 1 byte immediate data 12 bit address Addressing Mode 8 bit Displacement ST62T52C ST62T62C/E62C LOW 1110 1111 LDI 2 JRC a,(y) 0000 imm 1 prc 1 ind DEC 2 ...
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... ST62T52C ST62T62C/E62C 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V ...
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... Suffix 3. Suffix 4. & 6 Suffix 4. Suffix 4 4 & 6 Suffix version 3 Suffix version 1 & 6 Suffix version 3.6 4 4.5 5 SUPPLY VOLTAGE ( ST62T52C ST62T62C/E62C Value Unit Typ. Max °C 125 6.0 6.0 V 6.0 6.0 6.0 6.0 V 6.0 6.0 4.0 4.0 MHz 8.0 4.0 4.0 4.0 MHz 8.0 4 ...
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... ST62T52C ST62T62C/E62C 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125° C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input pins V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage ...
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... Acceptance (25° 55° 3. 4. VDD=5.0V (Except 626xB ROM) R=47k R=100k R=470k VDD=5.0V (626xB ROM) R=10k R=27k R=67k R=100k All Inputs Pins All Outputs Pins ST62T52C ST62T62C/E62C Value Unit Min. Typ. Max. V +50 mV 4.1 4 3.6 3 0.1 0.8 1.2 V 0.1 0.8 1.3 2.0 4.9 V 3.5 ...
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... ST62T52C ST62T62C/E62C 6.5 A/D CONVERTER CHARACTERISTICS (T = -40 to +125° C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input Current During AD I Conversion AC Analog Input Capacitance IN Notes: 1. Noise at VDD, VSS <10mV 2 ...
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... Figure 33. Vol versus Iol for High sink (30mA) I/Oports at T=25° This curves represents typical variations and is given for guidance only 20 30 Iol (mA Iol (mA Iol (mA) ST62T52C ST62T62C/E62C T = -40° 25° 95° 125° Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V 40 Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V 40 63/78 ...
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... ST62T52C ST62T62C/E62C Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd= This curves represents typical variations and is given for guidance only Figure 35. Voh versus Ioh on all I/O port at 25° This curves represents typical variations and is given for guidance only Figure 36 ...
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... Mhz for OTP devices 4V 5V Vdd for OTP devices 4V 5V Vdd for ROM devices 4V 5V Vdd ST62T52C ST62T62C/E62C T = -40° 25° 95° 125° -40° 25° 95° 125° -40° 25° ...
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... ST62T52C ST62T62C/E62C Figure 40. Idd WAIT versus V DD 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 41. Idd RUN versus This curves represents typical variations and is given for guidance only Figure 42. LVD thresholds versus temperature 4 ...
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... This curves represents typical variations and is given for guidance only Figure 44. RC frequency versus 0.1 3 This curves represents typical variations and is given for guidance only for ROM ST626xB only VDD (volts)] (Except for ST626xB ROM devices) DD 3.5 4 4.5 5 5.5 VDD (volts) ST62T52C ST62T62C/E62C R=1OK R=27K R=67K R=100K 6 R=47K R=100K R=470K 6 67/78 ...
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... ST62T52C ST62T62C/E62C 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 45. 16-Pin Plastic Dual In-Line Package, 300-mil Width Figure 46. 16-Pin Ceramic Side-Brazed Dual In-Line Package 68/ CDIP16W mm inches Dim. Min Typ Max Min Typ Max A 5.33 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0 ...
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... Figure 47. 16-Pin Plastic Small Outline Package, 300-mil Width Figure 48. 16-Pin Plastic Shrink Small Outline Package 45× Dim Dim ST62T52C ST62T62C/E62C mm inches Min Typ Max Min Typ Max A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 10 ...
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... ST62T52C ST62T62C/E62C THERMAL CHARACTERISTIC Symbol Parameter RthJA Thermal Resistance 7.2 ORDERING INFORMATION Table 22. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E62CF1 1836 EPROM ST62T52CM6 1836 OTP ST62T52CM3 ST62T62CM6 1836 OTP ST62T62CM3 ST62T52CB6 1836 OTP ST62T52CB3 ST62T62CB6 1836 OTP ST62T62CB3 ST62T52CN6 ...
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FASTROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER AND EEPROM 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125° C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...
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... ST62P52C ST62P62C 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P52C and ST62P62C are the Factory Advanced Service Technique ROM (FASTROM) version of ST62T52C and ST62T62C OTP devic- es. They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version ...
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ROM MCUs WITH A/D CONVERTER, SAFE RESET AUTO-RELOAD TIMER, ROM AND EEPROM 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125° C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up ...
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... ST6252C ST6262B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6252C and ST6262B are mask pro- grammed ROM version of ST62T52C and ST62T62C OTP devices. Figure 1. Programming Waveform 0.5s min TEST 15 14V typ 10 5 TEST 150 µs typ 100mA max 4mA typ 1.2 ROM READOUT PROTECTION If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to pre- vent any access to the program memory content ...
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... MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points ...
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... Enabled [ ] Enabled FASTROM Enabled ROM Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Enabled [ ] Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SUMMARY OF CHANGES Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) Changed f values in section 6.4 on page section 4.2 on page 41: vector #4 instead of vector #3 for the timer interrupt ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...