st62t62c STMicroelectronics, st62t62c Datasheet - Page 14

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st62t62c

Manufacturer Part Number
st62t62c
Description
8-bit Otp/eprom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom
Manufacturer
STMicroelectronics
Datasheet

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ST62T52C ST62T62C/E62C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
The two Option Bytes allow configuration capabili-
ty to the MCUs. Option byte’s content is automati-
cally read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
EPROM Code Option Byte (MSB)
D15-D13. Reserved. Must be cleared.
ADC SYNCHRO . When set, an A/D conversion is
started upon WAIT instruction execution, in order
to reduce supply noise. When this bit is low, an
A/D conversion is started as soon as the STA bit of
the A/D Converter Control Register is set.
D11. Reserved, must be cleared.
D10. Reserved, must be set to one.
NMI PULL. NMI Pull-Up . This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
LVD. LVD RESET enable. When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
PROTECT. Readout Protection. This bit allows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
EXTCNTL. External STOP MODE control. . When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When
14/78
PRO-
TECT
15
-
7
EXTC-
-
NTL
-
PB2-3
PULL
SYNCHRO
ADC
-
WDACT
-
LAY
DE-
-
OSCIL OSGEN
PULL
NMI
LVD
8
0
EXTCNTL is low, STOP mode is not available with
the watchdog active.
PB2-3 PULL. When set this bit removes pull-up at
reset on PB2-PB3 pins. When cleared PB2-PB3
pins have an internal pull-up resistor at reset.
D4. Reserved. Must be cleared to 0.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
DELAY. This bit enables the selection of the delay
internally generated after the internal reset (exter-
nal pin, LVD, or watchdog activated) is released.
When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
high.
OSCIL. Oscillator selection . When this bit is low,
the oscillator must be controlled by a quartz crys-
tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
OSGEN. Oscillator Safe Guard . This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode).
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/V
programming flow of the ST62T62C is described
in the User Manual of the EPROM Programming
Board.
The MCUs can be programmed with the
ST62E6xB EPROM programming tools available
from STMicroelectronics.
Table 5. ST62T52C/T62C Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from STMi-
croelectronics (ST62E6X-EPB or ST626X-KIT).
Device Address
0FFCh-0FFDh
0FA0h-0FEFh
0FF8h-0FFBh
0FFEh-0FFFh
0FF0h-0FF7h
0000h-087Fh
0880h-0F9Fh
NMI Interrupt Vector
Interrupt Vectors
Reset Vector
Description
User ROM
Reserved
Reserved
Reserved
PP
pin. The

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