st62t62cmae

Manufacturer Part Numberst62t62cmae
Description8-bit Otp/eprom/fastrom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom
ManufacturerSTMicroelectronics
st62t62cmae datasheet
 
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Page 41/72

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TIMER (Cont’d)
4.2.1 Timer Operation
The Timer prescaler is clocked by the prescaler
clock input (f
÷ 12).
INT
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#4 is generated. When the counter decrements to
Figure 26. Timer Working Principle
BIT0
BIT1
CLOCK
0
1
BIT0
BIT1
ST62T52CM-Auto ST62T62CM-Auto
zero, the TMZ bit in the TSCR register is set to
one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
7-BIT PRESCALER
BIT2
BIT3
BIT4
2
3
4
8-1 MULTIPLEXER
BIT2
BIT3
BIT4
8-BIT COUNTER
BIT5
BIT6
6
7
5
BIT7
BIT5
BIT6
VA00186
PS0
PS1
PS2
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