st62t62b STMicroelectronics, st62t62b Datasheet - Page 17

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st62t62b

Manufacturer Part Number
st62t62b
Description
8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer And Eeprom
Manufacturer
STMicroelectronics
Datasheet

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CLOCK SYSTEM (Cont’d)
Oscillator Control Registers
Address: DCh — Write only
Bit 7-4. These bits are not used.
Bit 3. Reserved. Cleared at Reset. THIS BIT
MUST BE SET TO 1 BY USER PROGRAM to
achieve lowest power consumption.
Bit 2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of
the Oscillator Divider in order to generate the in-
ternal frequency. The following selctions are avail-
able:
Figure 9. Clock Circuit Block Diagram
OSCout
OSCin
7
-
RS1
0
0
1
1
-
f
OSC
OSCILLATOR
-
MAIN
-
RS0
0
1
0
1
OSCR
3
f
OSC
OSCR
2
OSCILLATOR
Division Ratio
RS0, RS1
DIVIDER
RS1
1
2
4
4
RS0
0
Note: Care is required when handling the OSCR
register as some bits are write only. For this rea-
son, it is not allowed to change the OSCR con-
tents while executing interrupt service routine, as
the service routine cannot save and then restore
its previous content. If it is impossible to avoid the
writing of this register in interrupt service routine,
an image of this register must be saved in a RAM
location, and each time the program writes to
OSCR it must write also to the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
OSCR is not affected.
ST62T52B ST62T62B/E62B
f
INT
: 12
: 13
: 1
POR
Core
Timer
Watchdog
ADC
AR Timer
17/68
17

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