st62t65cm3 STMicroelectronics, st62t65cm3 Datasheet - Page 44

• Manufacturer Part Number: st62t65cm3
• Description: 8-bit Otp/eprom Mcus With A/d Converter, Safe Reset, Auto-reload Timer, Eeprom And Spi
• Manufacturer: STMicroelectronics

ST62T55C ST62T65C/E65C
TIMER (Cont’d)
4.2.1 Timer Operating Modes
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
the output mode.
4.2.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the
Timer clock input (f
signal on the TIMER pin is held high (allowing
pulse width measurement). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
PC1 must be configured in input mode
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
Figure 26. Timer Working Principle
44/86
CLOCK
INT
0
÷ 12 or TIMER pin signal), and to
BIT0
BIT0
INT
÷ 12), but ONLY when the
1
BIT1
BIT1
2
BIT2
BIT2
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT3
3
BIT3
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (f
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the TSCR and trans-
fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
Table 12. Timer Operating Modes
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is generated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR register is set to
one.
TOUT
BIT4
4
0
0
1
1
BIT4
DOUT
BIT5
0
1
0
1
5
BIT5
Input
Input
Output
Output
INT
Timer Pin
BIT6
÷ 12).
6
BIT6
BIT7
Event Counter
Gated Input
Output “0”
Output “1”
Timer Function
7
VA00186
PS0
PS1
PS2