st62t65b STMicroelectronics, st62t65b Datasheet - Page 51

• Manufacturer Part Number: st62t65b
• Description: 8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer, Eeprom And Spi
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
SPI DIV Register (DIV)
Address: E1h — Read/Write
Reset status: 00h
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register is set.
Bit 7 = SPINT: Interrupt Flag. It is automatically set
to one by the SPI at the end of a transmission or
reception and an interrupt request can be generat-
ed depending on the state of the interrupt mask bit
in the MOD control register. This bit is read-only
and must be cleared by user software at the end of
the interrupt service routine.
Bit 6-3 = DIV6-DIV3 : Burst Mode Bit Clock Period
Selection. Define thenumber of shiftregister bits that
are transmitted or received in a frame. The available
selections are listed in18. The normal maximum set-
ting is 8 bits, since the shift register is 8 bits wide.
Note that by setting a greater number of bits, in con-
junction with the SPIN bit in the MOD register, un-
wanted databits maybefilteredfromthe datastream.
Bit 2-0 = CD2-CD0: Base/Bit Clock Rate Selec-
tion . Define the division ratio between the core
clock (f
the Shift Register in Master mode.
Table 17. Base/Bit Clock Ratio Selection
Note : For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
Data setup time on Sin is typically 250ns min, while
data hold time is typically 50ns min.
0
0
0
0
1
1
1
1
SPINT
7
CD2-CD0
INT
DOV6
0
0
1
1
0
0
1
1
divided by 13) and the clock supplied to
DIV5
0
1
0
1
0
1
0
1
DIV4
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 256
Divide Ratio (decimal)
DIV3
CD2
CD1
CD0
0
Table 18. Burst Mode Bit Clock Periods
SPI Data/Shift Register (SPIDSR)
Address: E0h — Read/Write
Reset status: XXh
SPIDSR is read/write, however write access is not
allowed if the SPRUN bit of Mode Control register
is set to one.
Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA bits. The affect
of these setting is shown in the following diagrams.
The Shift Register transmits and receives the Most
Significant Bit first.
Bit 7-0 = DSR7-DSR0: Data Bits. These are the
SPI shift register data bits.
Miscellaneous Register (MISCR)
Address: DDh — Write only
Reset status: xxxxxxxb
Bit 7-1 = D7-D1 : Reserved.
Bit 0 = D0: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D7
7
7
-
DIV6-DIV3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D6
-
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D5
-
ST62T55B ST62T65B/E65B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D4
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Reserved (not to be used)
Number of bits sent
D3
-
Refer to the
description of the
DIV6-DIV3 bits in
the DIV Register
D2
-
D1
-
51/74
D0
D0
0
0
51