st52f510 STMicroelectronics, st52f510 Datasheet

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... High current sink/source in all pins Rev. 1.18 -June 2003 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. ST52F510/F513/F514 ST52F510/F513/F514 Two Timer/PWMs, ADC, I Peripherals On-chip 10-bit A/D Converter with 8 channel analog multiplexer and Autocalibration. 2 Programmable 16 bit Timer/PWMs with internal 16-bit Prescaler featuring: – ...

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... ST52F510/F513/F514 2/106 ...

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... Fast Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.3 Random data writing 4.2.4 Option Bytes Programming 4.3 Memory Verify .35 4.3.1 Fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3.2 Random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 Memory Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.5 ID Code .37 4.6 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.7 In-Situ Programming (ISP .38 4.8 In-Application Programming (IAP .38 4.8.1 Single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8.2 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8.3 Memory Corruption Prevention 4.8.4 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.8.5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ST52F510/F513/F514 3/106 ...

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... ST52F510/F513/F514 5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.4 Interrupt Maskability and Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.5 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6 CLOCK, RESET & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6.2 Reset .45 6.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.2 Reset Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 Programmable Low Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.4 Power Saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.4.1 Wait Mode ...

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... SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 13.1.1 Recovery Buffer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1.2 SCDR_RX Block 13.2 SCI Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 13.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 13.4 SCI Register Description .84 13.4.1 SCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.4.2 SCI Input Registers 13.4.3 SCI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14 I2C BUS INTERFACE (I2C 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 14.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 14.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 ST52F510/F513/F514 5/106 ...

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... ST52F510/F513/F514 14.3.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.3.2 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.3.3 SDA/SCL Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 14.4.1 Slave Mode 14.4.2 Master Mode 14.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 14.5.1 I2C Interface Configuration Registers 14.5.2 I2C Interface Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.5.3 I2C Interface Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 15 SERIAL PERIPHERAL INTERFACE (SPI 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 15.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 15.3 General description .96 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 15.4.1 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 15 ...

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... Non-Maskable Interrupt, which has fixed top level priority. Two versatile Port Interrupts are available for synchronization with external sources. The ST52F510/F513/F514 also include an on-chip Power-on-Reset (POR), which provides an internal chip reset during power up situation and a Programmable Low Voltage Detector (PLVD), ...

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... Memory Programming Mode, the Vpp pin must be tied to Vdd. A RESET signal must be applied to the device to switch from one mode to the other. 1.2.1 Memory Programming Mode. The ST52F510/F513/F514 memory is loaded in the Memory Programming Mode. All instructions and data are written inside the memory during this phase. 8/106 The Option Bytes are loaded during this phase by using the programming tools ...

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... Legend: Sales code: ST52tnnncmpy Memory type (t): F=FLASH Subfamily (nnn): 510, 513, 514 Pin Count (c): Y=16 pins, F=20 pins, G=28 pins, K=32/34 pins 2=4 Kb, 3=8 Kb Flash (ST52F510 & ST52F513) Memory Size (m): 1=1024, 3=4096 EEPROM (only ST52F514) Packages (p): B=PDIP, M=PSO, T=TQFP Temperature (y): 0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105 RAM EEPROM ...

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... ST52F510/F513/F514 Figure 1.1 ST52F510/F513/F514 Block Diagram MEMORY FLASH ISP/IAP DATA RAM 256 bytes DATA EEPROM MEMORY INTERFACE CORE ALU & DPU DECISION PROCESSOR CONTROL UNIT Register File 256 bytes PC POWER SUPPLY & PLVD VDD VPP 10/106 PORT A TIMER/PWM 0 TIMER/PWM 1 PORT B Input registers ...

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... Figure 1.2 ST52F510/F513/F514 SO20/DIP20 Pin Configuration 1 Vdd OscOut 2 SO20 OscIn 3 Vpp 4 5 PB0/VREF/AIN0 6 PB1/AIN1 PB2/AIN2 7 8 PB3/AIN3 PB4/AIN4 9 PB5/AIN5 10 Figure 1.3 ST52F510/F513/F514 SO16 Pin Configuration Vdd OscOut OscIn Vpp PB0/VREF/AIN0 PB1/AIN1 PA7/INT PA6/T0OUT 1 20 Vdd Vss OscOut RESET 19 2 PA0/SCL OscIn 18 3 PA1/SDA ...

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... ST52F510/F513/F514 Figure 1.4 ST52F510/F513/F514 SDIP32/DIP28 Pin Configuration Vdd 1 VddIO 2 SDIP32 OscOut 3 OscIn 4 Vpp 5 PB0/VREF/AIN0 6 PB1/AIN1 7 PB2/AIN2 8 PB3/AIN3 9 PB4/AIN4 10 PB5/AIN5 11 PB6/AIN6 12 PB7AIN7 13 PC0/SCK 14 PC1/MOSI 15 N.C. 16 12/106 Vss 32 Vdd 1 VssIO 31 OscOut 2 RESET 30 OscIn 3 PA0/SCL 29 Vpp 4 PA1/SDA 28 PB0/VREF/AIN0 5 PA2/T1OUT 27 PB1/AIN1 6 PA3/RX 26 PB2/AIN2 7 PA4/TSTRT 25 PB3/AIN3 8 PA5/TCLK/TX ...

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... Table 1.2 ST52F510/F513/F514 SDIP32 Pin List SDIP32 NAME 1 Vdd 2 VddIO 3 OSCOUT 4 OSCIN 5 Vpp Programming Mode Selector 6 PB0/VREF/AIN0 7 PB1/AIN1 8 PB2/AIN2 9 PB3/AIN3 10 PB4/AIN4 11 PB5/AIN5 12 PB6/AIN6 13 PB7/AIN7 14 PC0/SCK 15 PC1/MOSI 16 N.C 17 N.C 18 PC2/MISO 19 PC3/SS 20 PC4/TX 21 PC5/TRES 22 PA7/INT 23 PA6/T0OUT 24 PA5/TCLK/TX 25 PA4/TSTRT 26 PA3/RX 27 PA2/T1OUT 28 PA1/SDA 29 PA0/SCL 30 RESET 31 VssIO 32 Vss ...

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... ST52F510/F513/F514 Table 1.3 ST52F510/F513/F514 SO28 Pin List SO28 NAME 1 Vdd 2 OSCOUT 3 OSCIN 4 Vpp Programming Mode Selector 5 PB0/VREF/AIN0 6 PB1/AIN1 7 PB2/AIN2 8 PB3/AIN3 9 PB4/AIN4 10 PB5/AIN5 11 PB6/AIN6 12 PB7/AIN7 13 PC0/SCK 14 PC1/MOSI 15 PC2/MISO 16 PC3/SS 17 PC4/TX 18 PC5/TRES 19 PA7/INT 20 PA6/T0OUT 21 PA5/TCLK/TX 22 PA4/TSTRT 23 PA3/RX 24 PA2/T1OUT 25 PA1/SDA 26 PA0/SCL 27 RESET 28 Vss 14/106 Programming Phase ...

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... Table 1.4 ST52F510/F513/F514 SO20/DIP20/SO16 Pin List SO20 SO16 NAME DIP20 1 1 Vdd 2 2 OSCOUT 3 3 OSCIN 4 4 Vpp 5 5 PB0/VREF/AIN0 6 6 PB1/AIN1 7 - PB2/AIN2 8 - PB3/AIN3 9 - PB4/AIN4 10 - PB5/AIN5 11 7 PA7/INT 12 8 PA6/T0OUT 13 9 PA5/TCLK/ PA4/TSTRT 15 11 PA3/ PA2/T1OUT 17 13 PA1/SDA 18 14 PA0/SCL ...

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... Without any connection, the device can work with its internal clock generator (10 MHz) RESET. This signal is used to reset the ST52F510/ F513/F514 and re-initialize the registers and control signals also used when switching from the Programming Mode to Working Mode and vice versa ...

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... INTERNAL ARCHITECTURE ST52F510/F513/F514’s architecture is Register File based and is composed of the following blocks and peripherals: Control Unit (CU) Data Processing Unit (DPU) Decision Processor (DP) ALU Memory Interface up to 256 bytes Register File Program/Data Memory Data EEPROM Interrupts Controller Clock Oscillator PLVD and POR ...

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... ST52F510/F513/F514 Figure 2.2 Data Processing Unit (DPU) Interrupts Unit Program Memory Input Registers Peripherals REGISTER FILE ADDRESS The DPU receives, stores and sends the instructions deriving from the Program/Data Memory, Register File or from the peripherals controlled by the CU on the basis of the decoded instruction ...

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... Chapter 9 Instruction Set for further details). In addition, the ALU of ST52F510/F513/F514 can perform multiplication (MULT) and division (DIV). Multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values); the ...

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... ST52F510/F513/F514 2.3 Register Description Flags Register (FLAG) Input Register 38 (026h) Read Only Reset Value: 0000 0000 (00h Bit 7-3: Not Used Bit 2: Z Zero flag Bit 1: S Sign flag Bit 0: C Carry flag 20/106 ...

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... System and User Stacks. STFive CORE REGISTER FILE DECISION LDFR PROCESSOR REGISTERS LDPR LDCNF GETPG PGSETR PROGRAM COUNTER INPUT REGISTERS LDRI CU DPU ALU ST52F510/F513/F514 Register File and the other ON CHIP PERIPHERALS OUTPUT REGISTERS PERIPHERAL BLOCK PERIPHERAL CONFIGURATION BLOCK REGISTERS LDCR PERIPHERAL BLOCK ...

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... Mbf data through the last NVM address) contains the instruction of the user program and the permanent data. Option bytes block (from location 307Fh) is the addressing space reserved for the option bytes. In ST52F510/F513/F514, only the location from 3000h to 3007h are used OPTION BYTES ...

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... PC is stored in a couple of locations pointed to by the SSP that is decreased by 2. PROGRAM COUNTER RETI LOCATION ADRESS PAGE NUMBER IRQ REGISTER FILE POP X CONFIGURATION REGISTERS PUSH X USER STACK TOP LSB USER STACK TOP MSB ST52F510/F513/F514 LSB MSB REGISTER X 23/106 ...

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... The current SSP can be read and write in the couple of Configuration Registers 44 02Ch (MSB: page number, always 32 020h) and 45 02Dh (LSB: location address) (see Figure 3.3). In ST52F510/ F513/F514 the user can only consider the LSB because the MSB is always the same. The User Stack is used to store user data and is ...

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... In order to simplify the concept, a mnemonic name the following is assigned to each register. The same name is used in Visual FIVE development tools. The list of the Configuration Registers is shown in Table 3.4. ST52F510/F513/F514 the Configuration Register the Configuration Register Register File location ...

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... ST52F510/F513/F514 Table 3.1 Input Registers Mnemonic PORT_A_IN PORT_B_IN PORT_C_IN - - SPI_IN I2C_IN I2C_SR1 I2C_SR2 - - USP_H USP_L - PWM0_COUNT_IN_H PWM0_COUNT_IN_L PWM0_STATUS PWM0_CAPTURE_H PWM0_CAPTURE_L PWM1_COUNT_IN_H PWM1_COUNT_IN_L PWM1_STATUS PWM1_CAPTURE_H PWM1_CAPTURE_L - SCI_IN SCI_STATUS FLAGS AD_OVF IAP_SR 26/106 Description Port A data Input Register Port B data Input Register Port C data Input Register ...

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... A/D Converter Channel 5 data Input Register (MSB) 10-bit A/D Converter Channel 5 data Input Register (LSB) 10-bit A/D Converter Channel 6 data Input Register (MSB) 10-bit A/D Converter Channel 6 data Input Register (LSB) 10-bit A/D Converter Channel 7 data Input Register (MSB) 10-bit A/D Converter Channel 7 data Input Register (LSB) ST52F510/F513/F514 Address 41 029h 42 02Ah ...

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... ST52F510/F513/F514 Table 3.2 Output Registers Mnemonic PORT_A_OUT PORT_B_OUT PORT_C_OUT - - SPI_OUT I2C_OUT PWM0_COUNT_OUT_H PWM0_COUNT_OUT_L PWM0_RELOAD_H PWM0_RELOAD_L PWM1_COUNT_OUT_H PWM1_COUNT_OUT_L PWM1_RELOAD_H PWM1_RELOAD_L SCI_OUT Table 3.3 Option Bytes Mnemonic OSC_CR CLK_SET OSC_SET PLDV_CR WDT_EN PG_LOCK PG_UNLOCK WAKEUP 28/106 Description Port A data Output Register Port B data Output Register ...

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... C Interface Own Address Register Interface Own Address Register 2 Serial Peripheral Interface Control Register Serial Peripheral Interface Control-Status Register Serial Communication Interface Control Register 1 Serial Communication Interface Control Register 2 Port A Pull Up enable/disable Register Port A Option Register ST52F510/F513/F514 Address 0 00h 1 01h 2 02h 3 03h ...

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... ST52F510/F513/F514 Table 3.4 Configuration Registers Mnemonic PORT_A_DDR PORT_A_AF PORT_B_PULLUP PORT_B_OR PORT_B_DDR PORT_B_AF PORT_C_PULLUP PORT_C_OR PORT_C_DDR PORT_C_AF - SCI_CR3 SSP_H SSP_L CPU_CLK AD_CR2 30/106 Description Port A Data Direction Register Port A Alternate Function selection Register Port B Pull Up enable/disable Register Port B Option Register Port B Data Direction Register ...

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... MEMORY PROGRAMMING ST52F510/F513/F514 provides an on-chip user programmable non-volatile memory, which allows fast and reliable storage of user data. Program/Data Memory addressing space is composed by a Single Voltage Flash Memory and a RAM memory bench. The ST52F513/514 devices also have a Data EEPROM bench to store permanent data with long term retention and a high number of write/erase cycles ...

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... ST52F510/F513/F514 4.2 Memory Programming The Programming procedure writes the user program and data into the Flash Memory, EEPROM and Option Bytes. The programming procedures are entered by setting the V equal to V and releasing the Reset signal. The dd following pins are used in Programming mode: ...

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... The second byte is the data to be written 6. The device held the SCL line low until the data is not stored in the memory (about 4.5 ms for erasing and 2.5 for writing) ST52F510/F513/F514 DataN ..... DataN A ...

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... ST52F510/F513/F514 A similar procedure can be used to write a single block: 1. The SetPage command is sent, followed by the page number where the data should be written 2. The IncBlock command is sent as many times as the block number inside the page (for ex- ample: to address the block 3 the IncBlock must be sent 3 times) 3 ...

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... The sequence restarts from point 3 until there is data to be read. Remark: for the same reasons explained in Section 4.2.4 the Option Bytes cannot be read with this procedure: they can be read with a direct addressing procedure as the one explained in the next section. ST52F510/F513/F514 A Data read NA P ..... ..... Data read 10100001 A ...

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... ST52F510/F513/F514 4.3.2 Random data reading. To read a specified memory location, the following procedure should be used: 1. The Programming mode is entered with the sequence described in Section 4.2.1 2. The SetPage command is sent, followed to the page number where the data to be read is located 3. The ByteRead command is sent, followed by an address inside the page 4 ...

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... The data sent by the Master hasn’t been received correctly by the device The Master sent a wrong command code A command not allowed when the device is locked has been sent A code different form the Programming mode code (00000000) has been sent ST52F510/F513/F514 A Status Byte NA P the ...

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... The ISP can be applied by using the standard tools for the device programming.The ISP can be applied by using the standard tools for the device programming. The ST52F510 Starter Kit supplies a cable to perform the ISP. The user application board should supply a suited connector type for the cable (see Starter Kit User Manual) ...

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... Bit 0: ABRT Writing operation aborted 0: The writing has been completed 1: The writing has been aborted because an interrupt or another unspecified cause occurred. 0 The ABRT and PRTCD bits are reset after the next successful data writing in the Flash of EEPROM memory. ST52F510/F513/F514 PRTCD ABRT 39/106 ...

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... ST52F510/F513/F514 5 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events through its interrupt channels. When such events occur, if the related interrupt is not masked and doesn’t have a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine ...

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... Interrupt Sources ST52F510/F513/F514 manages interrupt signals generated by the internal peripherals or generated by software by the TRAP instruction or coming from the Port pins. There are two kinds of interrupts coming from the Port pins: the NMI and the Ports Interrupts. NMI (Not Maskable Interrupt) is associated with pin PA7 when it is configured as Alternate Function. This interrupt source doesn’ ...

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... ST52F510/F513/F514 5.6 Register Description Interrupt Mask Register (INT_MASK) Configuration Register 0 (00h) Read/Write Reset Value: 0000 0000 (00h) 7 MSKPB MSKPA MSKI2C MSKSPI MSKSCI MSKT1 Bit 7: MSKPB Interrupt Mask Port B 0: Port B interrupt masked 1: Port B interrupt enabled Bit 6: MSKPA Interrupt Mask Port A 0: Port A interrupt masked ...

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... Warning: the Priority Level configuration registers must be always configured. PRL code RINT code 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 ST52F510/F513/F514 Maskable Vector Addresses Yes 3-5 (03h-05h) Yes 6-8 (06h-08h) Yes 9-11 (09h-0Bh) Yes 12-14 (0Ch-0Eh) Yes 15-17 (0Fh-011h) Yes 18-20 (012h-014h) Yes 21-23 (015h-017h) Yes 24-26 (018h-01Ah) No 27-29 (01Bh-01Dh) No 30-32 (01Eh-020h) 43/106 ...

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... ST52F510/F513/F514 Clock module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals. The Clock is designed to require a minimum of external components. ST52F510/F513/F514 devices supply the internal oscillator in four clock modes: External oscillator External clock External RC oscillator Internal clock The device always starts in internal clock mode, excluding any external clock source ...

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... W ATCHDOG CKMOD1:0 INTERNAL CLOCK SOURCES (W AKEUP+1) x EXTERNAL CLOCK 4096 x TCLK PROGRAMMABLE LOW VOLTAGE DETECTOR RESET PLVD TCLK = Internal Clock period (100 ns) CKMOD1:0 = see Option Byte 0 (OSC_CR) W AKEUP = see Option Byte 7 (W AKEUP) ST52F510/F513/F514 WAKEUP + 1 Tclk Assembler tool automatically INTERNAL RESET 45/106 ...

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... ST52F510/F513/F514 6.3 Programmable Low Voltage Detector The on-chip Programmable Low Voltage Detector (PLVD) circuit prevents the processor from falling into an unpredictable status if the power supply drops below a certain level. When Vdd drops below the detection level, the PLVD causes an internal processor Reset that remains active as long as Vdd remains below the trigger level ...

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... OFF PERIPHERALS CLOCK OFF CPU CLOCK OFF YES NO NMI or PORT INTERRUPT ON OSCILLATOR ON PERIPHERALS CLOCK ON CPU CLOCK YES YES ST52F510/F513/F514 YES PORT INTERRUPT MASKED 4096 INTERNAL CLOCK CYCLES DELAY INTERNAL CLOCK ? NO 4096 X (WAKEUP+1) CLOCK CYCLES DELAY RESTART PROGRAM SERVICING THE ...

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... ST52F510/F513/F514 6.5 Register Description The following section describes the Register which are used to configure the Clock, Reset and PLVD. 6.5.1 Configuration Register. CPU Clock Prescaler (CPU_CLK) Configuration Register 46 (02Eh) Read/Write Reset Value: 0000 0000 (00h CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0 Bit 7-6: Not Used ...

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... External Reset or a POR and after the wake-up from Halt. The time delay is computed according to the following formula: Delay = 0 Warning: If the internal clock is used as clock source the prescaler is not used. - PLVD1 PLVD0 ST52F510/F513/F514 Settling Times for 40% duty-cycle - - ...

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... Introduction ST52F510/F513/F514 are characterized flexible individually programmable multi-functional I/O lines. The ST52F510/F513/F514 supplies devices with Ports (named from with I/O lines. Each pin can be used as a digital I/O or can be connected with a peripheral (Alternate Function). The I/O lines belonging to Port A and Port B can also be used to generate Port Interrupts ...

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... Each bit of the configuration registers configures the pin of the corresponding position (example: PORT_A_DDR bit 5 configures the pin PA5). EN SEL PU INT ENABLE DATA TO INPUT REGISTER ST52F510/F513/F514 2 C peripheral, directly drive the Registers PORT_x_PULLUP, and PORT_x_DDR must be the pin’s configuration, Vdd ...

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... ST52F510/F513/F514 7.6.1 Configuration Registers. Port A Pull-Up Register (PORT_A_PULLUP) Configuration Register 24 (018h) Read/Write Reset Value: 0000 0000 (00h) 7 PUA7 PUA6 PUA5 PUA4 PUA3 Bit 7-0: PUA7-0 Port A pull-up (see Table 7.1) 0: Port A pin without pull-up 1: Port A pin with pull-up Port A Option Register (PORT_A_OR) Configuration Register 25 (019h) Read/Write ...

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... Port C Pull-Up Register (PORT_C_PULLUP) Configuration Register 32 (020h) Read/Write Reset Value: 0000 0000 (00h Note: This register is not used in 16/20 pin devices 0 Bit 7-6: Not Used AFB2 AFB1 AFB0 Bit 5-0: PUC5-0 Port C pull-up (see Table 7.1) 0: Port C pin without pull-up ST52F510/F513/F514 PUC5 PUC4 PUC3 PUC2 PUC1 PUC0 53/106 0 ...

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... ST52F510/F513/F514 1: Port C pin with pull-up Port C Option Register (PORT_C_OR) Configuration Register 33 (021h) Read/Write Reset Value: 0000 0000 (00h ORC5 ORC4 ORC3 ORC2 Note: This register is not used in 16/20 pin devices Bit 7-6: Not Used Bit 5-0: ORC5-0 Port C option (see Table 7.1) Port C Data Direction Register (PORT_C_DDR) ...

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... Note: This register is not used in 16/20 pin devices Bit 7-6: Not Used Bit 5-0: PCO5-0 Port C Input data 0 PAO2 PAO1 PAO0 The logical values written in these register bits are put in the Port C pins configured as digital output. ST52F510/F513/F514 PBO5** PBO4** PBO3** PBO2** PBO1 PBO0 PCO5 PCO4 PCO3 PCO2 PCO1 ...

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... Program/Data Memory size. 8.1 Fuzzy Inference The block diagram shown in Figure 8.1 describes the different steps performed during a Fuzzy algorithm. The ST52F510/F513/F514 Core allows for the implementation of a Mamdami type fuzzy inference with crisp consequents. Inputs for fuzzy inference are stored in 8 dedicated Fuzzy input registers ...

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... By using the previous memorization method different kinds of triangular Membership Functions may be stored. Figure 8.5 shows some examples of valid Mbfs that can be defined in ST52F510/ F513/F514. Each Mbf is then defined storing 3 bytes in the first Kbyte of the Program/Data Memory. ...

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... ST52F510/F513/F514 Figure 8.5 Example of valid Mbfs 8.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn’t have a shape, like a traditional Mbf, and is characterized by a single point identified by the couple (X, w), where w is calculated by the Inference Unit as described earlier ...

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... Mbf and stores the result in internal registers 1 6 value of Input with Mbf and stores the result in internal registers 6 14 operation with the crisp value crisp ST52F510/F513/F514 NOT Mbf ) THEN Crisp 59/106 ...

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... ST52F510/F513/F514 9 INSTRUCTION SET ST52F510/F513/F514 supplies 107 ( Fuzzy) instructions that perform computations and control the device. Computational time required for each instruction consists of one clock pulse for each Cycle plus 2 clock pulses for the decoding phase. Total computation time for each instruction is reported in Table 9 ...

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... Arithmetic Instructions Bytes Cycles ST52F510/F513/F514 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ...

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... ST52F510/F513/F514 DIV DIV regx, regy INC INC regx MIRROR MIRROR regx MULT MULT regx, regy NOT NOT regx OR OR regx, regy ORI ORI regx, const SUB SUB regx, regy SUBI SUBI regx, const SUBIS SUBIS regx, const SUBO SUBO regx, regy ...

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... Jump Instructions Bytes Cycles 5/6 3 5/6 3 5/6 3 5/6 3 5 Bytes Cycles 1 4/ 7/10 Control Instructions Bytes Cycles ST52F510/F513/F514 ...

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... ST52F510/F513/F514 Notes: regx, regy: Register File Address memx, memy: Program/Data Memory Addresses confx, confy: Configuration Registers Addresses outx: Output Registers Addresses inpx: Input Registers Addresses const: Constant value fuzzyx: Fuzzy Input Registers I flag affected - flag not affected (*) The instruction BLKSET determines the start byte block writing in Flash or EEPROM Program/ Data Memory ...

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... A/D CONVERTER 10.1 Introduction ST52F510/F513/F514 A/D Converter is a 10-bit analog to digital converter with analog inputs. The A/D converter offers a typical conversion time fast mode and slow mode. This period also includes the time of the integral Sample and Hold circuitry, which ...

Page 66

... The bit is reset at the next conversion having no overflow occurrence. ST52F510/F513/F514 Interrupt Unit provides one maskable channel for the End of Conversion and for the overflow control possible to set the interrupt source on EOC or on overflow or on both by programming the INT0 and INT1 bits in the AD_CR Configuration Registers ...

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... External from VREF pin 0 Bit 2: RESOL 8/10 bits resolution POW CONT STR 0: 10 bits 1: 8 bits Bit 1: INT1 Overflow interrupt mask 0: interrupt disabled 1: interrupt enabled (if MSKAD=1) Bit 0: INT0 End of Conversion interrupt mask 0: interrupt disabled 1: interrupt enabled (if MSKAD=1) ST52F510/F513/F514 0 - PRECH REF RESOL INT1 INT0 67/106 ...

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... ST52F510/F513/F514 10.5.2 Input Registers. A/D Converter Overflow Register (AD_OVF) Input Register 39 (027h) Read only Reset Value: 0000 0000 (00h) 7 OVF7 OVF6 OVF5 OVF4 OVF3 Bit 7-0: OVF7-OVF0 Overflow Flag 0: no overflow occurred in the last conversion 1: overflow occurred in the last conversion A/D Converter Data Registers The converted digital values of the analog level ...

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... Once the WDT is activated, the application program has to refresh the counter (by the WDTRFR instruction) during normal operation in order to prevent an ICU reset. In ST52F510/F513/F514 devices it is possible to choose between “Hardware” Watchdog. The Hardware WDT allows the counting to avoid unwanted stops for external interferences ...

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... ST52F510/F513/F514 Watchdog Control Register (WDT_CR) Configuration Register 7 (07h) Read/Write Reset Value: 0000 0001 (00h Bit 7-4: Not Used Table 11.2 Watchdog Timeout configuration examples WDT_CR(3:0) Division Factor 0000 1 0001 625 0010 1250 0011 1875 0100 2500 0101 3125 0110 3750 0111 4375 ...

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... PWM/TIMERS 12.1 Introduction ST52F510/513/514 offers two on-chip PWM/Timer peripherals. All ST52F510/513/514 PWM/Timers have the same internal structure. The timer consists of a 16-bit counter with a 16-bit programmable Prescaler, giving a maximum count (see Figure 12.1). Each timer has two different working modes, which can be selected by setting the correspondent bit ...

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... ST52F510/F513/F514 Figure 12.2 Timer 0 External Start/Stop Mode start Level start E dge R eset C lock C ounted 0 V alue TxSTRT signal starts/stops the Timer from counting only if the peripherals are configured in Timer mode. The Timers are started by writing 1 in the TXSTRT bit of the PWMx_CR1 and are stopped by writing 0 ...

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... Counter value. The same recommendation is made when reading the two bytes of the counter performed in two steps the timer is running, the carry of the LSB to the MSB can cause the wrong 16-bit value reading. A Reload value greater than 1 must always be used. ST52F510/F513/F514 PWMxCOUNT on ...

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... ST52F510/F513/F514 When the Timers are in Reset status, or when the device is reset, the TxOUT pins goes in threestate. If these outputs are used to drive external devices recommended that the related pins be left in the default configuration (Input threestate) or change them in this configuration. In PWM mode the PWM/Timers can only be Set or Reset: Start/Stop signals do not affect the Timers ...

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... Input Register 21 (015h) Read only Reset Value: 0000 0000 (00h) 7 T0CI15 T0CI14 Bit 7-0: T0CI15-8 PWM/Timer 0 Counter MSB In this register the current value of the Timer 0 Counter MSB can be read. ST52F510/F513/F514 - RESPOL STRPOL POLPB POLPA POLNMI T0CI13 T0CI12 T0CI11 T0CI10 T0CI9 T0CI8 ...

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... ST52F510/F513/F514 PWM/Timer 0 Counter Low Input Register (PWM0_COUNT_IN_L) Input Register 22 (016h) Read only Reset Value: 0000 0000 (00h) 7 T0CI7 T0CI6 T0CI5 T0CI4 T0CI3 T0CI2 Bit 7-0: T0CI7-0 PWM/Timer 0 Counter MSB In this register the current value of the Timer 0 Counter LSB can be read. PWM/Timer 0 Status Register (PWM0_STATUS) ...

Page 77

... Bit 4: T1IER Interrupt on T1OUT rising Enable 0: interrupt disabled 1: interrupt enabled Bit 3: not used 0 Bit 2: T1STRT PWM/Timer 1 Start bit 0: Timer 0 stopped 1: Timer 0 started Bit 1: not used Bit 0: T1RES PWM/Timer 1 Reset bit 0: PWM/Timer 0 reset register, the 1: PWM/Timer 0 set ST52F510/F513/F514 T1IEF T1IER - T1STRT - T1RES 77/106 0 ...

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... ST52F510/F513/F514 PWM/Timer 1 Control Register 2 (PWM1_CR2) Configuration Register 13 (0Dh) Read/Write Reset Value: 0000 0000 (00h T1WAV T1PRESC Bit 7-6: Not Used Bit 5: T1WAV T1OUT Waveform 0: pulse (type2) 1: square (type1) Bit 4-0: T1PRESC PWM/Timer 1 Prescaler The PWM/Timer 1 clock is divided by a T1PRESC factor equal to 2 value allowed for T1PRESC is 10000 (010h) ...

Page 79

... This register is used to write the Timer 1 Reload value (LSB). Note: by writing PWM1_RELOAD_x couple is latched in the internal registers of the peripherals. For this reason, this register should be written after the 0 MSB one. T1CO1 T1CO0 ST52F510/F513/F514 this register, the 0 0 this register, the 79/106 ...

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... ST52F510/F513/F514 13 SERIAL COMMUNICATION INTERFACE The Serial Communication integrated into ST52F510/F513/F514 provides a general purpose shift register peripheral, several widely distributed devices to be linked, through their SCI subsystem. SCI gives a serial interface providing communication with the speed from less than 300 up to over 115200 baud, and a flexible character format ...

Page 81

... Figure 13.3 SCI Status Register SCI_STATUS Input Register ST52F510/F513/F514 The procedure described above, allows SCI not to becomes IDLE, because of a limited noise due to an erroneous sampling, the transmission is recognized as correct and the noise flag error is set ...

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... ST52F510/F513/F514 13.2 SCI Transmitter Block The SCI Transmitter Block consists of the following blocks: SCDR_TX and SHIFT synchronized, respectively, with the clock master signal (CKM) and the CLOCK_TX. The whole block receives the settings for the following transmission modes Configuration Register: 8 bit length, 1 stop bit, no parity bit ...

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... ST52F510/F513/F514 833 1042 1250 417 521 625 208 260 313 78 104 130 156 ...

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... ST52F510/F513/F514 13.4 SCI Register Description The following registers are related to the use of the SCI peripheral. 13.4.1 SCI Configuration Registers. SCI Control Register 1 ( SCI_CR1 Configuration Register 22 (016h) Read/Write Reset Value: 0000 0000 (00h) 7 RXFINT OVRINT BRKINT TXEMINT TXENINT PAR/T8 Bit 7: RXFINT SCDR_RX buffer full interrupt mask ...

Page 85

... SCI Output Register. R8 TXEM TXEND SCI TX data Output Register (SCI_OUT) Input Register 23 (017h) Write only Reset Value: 0000 0000 (00h) 7 TX7 TX6 Bit 7-0: TX7-0 TX Data In this register the serial data to be transmitted can be written. ST52F510/F513/F514 0 TX5 TX4 TX3 TX2 TX1 TX0 85/106 ...

Page 86

... ST52F510/F513/F514 BUS INTERFACE (I C) 14.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I providing both multimaster and slave functions and 2 controls all I C bus-specific sequencing, protocol, arbitration and timing. The 2 supports fast I C mode (400kHz). ...

Page 87

... SDA line and sent to the shift register; then it is compared with the 2 C bus mode. address of the interface or the General Call address (if selected by software). DATA REGISTER DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER (OAR) CONTROL LOGIC INTERRUPT ST52F510/F513/F514 2 C interface operates in Slave 87/106 ...

Page 88

... ST52F510/F513/F514 Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledgement pulse if the ACK bit is set. Address not matched : the interface ignores it and waits for another Start condition ...

Page 89

... I2C_SR1 register followed by a read of the I2C_IN register, holding the SCL line low (see Figure 14.3 Transfer sequencing EV7). ST52F510/F513/F514 In order to close the communication: before reading the last byte from the I2C_IN register, set the STOP bit to generate the Stop condition. The interface automatically goes back to slave mode (M/SL bit cleared) ...

Page 90

... ST52F510/F513/F514 Figure 14.3 Tranfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A Data1 EV5 EV6 7-bit Master transmitter: S Address A EV5 EV6 EV8 10-bit Slave receiver: S Header A Address A EV1 10-bit Slave transmitter: S Header ...

Page 91

... Note: The I C interrupt events are connected to the same interrupt vector. They generate an interrupt if the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK Configuration Register is unmasked (set to 1, see Interrupts Chapter). ST52F510/F513/F514 ITE Enable Event ...

Page 92

... ST52F510/F513/F514 14.5 Register Description In the following sections describe the registers 2 used by the I C Interface are described. 2 14.5 Interface Configuration Registers Control Register (I2C_CR) Configuration Register 16 (010h) Read/Write Reset Value: 0000 0000 (00h ENGC START Bit 7-6: Not Used. They must be held to 0. ...

Page 93

... Then, the next data bytes are received one by one after reading the I2C_IN register Status Register 1 (I2C_SR1) Input Register 7 (07h) Read only Reset Value: 0000 0000 (00h EVF ADD10 ST52F510/F513/F514 ADD9 ADD8 I2CDI5 I2CDI4 I2CDI3 I2CDI2 I2CDI1 I2CDI0 ...

Page 94

... ST52F510/F513/F514 Bit 7: EVF Event Flag This bit is set by hardware as soon as an event occurs cleared by software reading I2C_SR2 register in case of error event or as described in Figure 14. also cleared by hardware when the interface is disabled (PE=0 event 1: One of the following events has occurred: – ...

Page 95

... Reset Value: 0000 0000 (00h) 7 I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0 bit 7-0: I2CDO7-I2CDO0 Data to be transmitted. These bits contain the byte to be transmitted in the bus in Transmitter mode: Byte transmission start automatically when the software writes in the I2C_OUT register. ST52F510/F513/F514 0 95/106 ...

Page 96

... ST52F510/F513/F514 15 SERIAL PERIPHERAL INTERFACE (SPI) 15.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master, one or more slaves system, in which devices may be either masters or slaves. SPI is normally used for communication between the ICU and external peripherals or another ICU ...

Page 97

... Clearing the SPIF bit is performed by the following software sequence access to the SPI_STATUS_CR register while the SPIF bit is set 2. A read to the SPI_IN register. Note: While the SPIF bit is set, all writes to the SPI_OUT register SPI_STATUS_CR register is read. ST52F510/F513/F514 IT request SPI_STATUS_CR OR MODF SOD SSM SSI ...

Page 98

... ST52F510/F513/F514 15.4.2 Slave Configuration. In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0, SPR1 and SPR2 bits is not used for data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the master de- vice (CPOL and CPHA bits). See Figure 15.4. – ...

Page 99

... MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. Byte 1 Byte 2 ST52F510/F513/F514 Byte 3 99/106 ...

Page 100

... ST52F510/F513/F514 Figure 15.4 Data Clock Timing Diagram CPOL = 1 CPOL = 0 MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MISO MSBit Bit 6 (from master) MOSI MSBit Bit 6 (from slave) SS (to slave) CAPTURE STROBE Note: This figure should not be used as a replacement for parametric information. ...

Page 101

... I/O ports exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPI_CR register and the MODF bit in the SPI_STATUS_CR register. ST52F510/F513/F514 THEN SPIF =0 WCOL transfer has started WCOL=1 ...

Page 102

... ST52F510/F513/F514 Figure 15.6 Single Master Configuration SS SCK Slave MCU MOSI MISO MOSI MISO SCK Master MCU 5V SS 15.4.8 Interrupts Interrupt Event SPI End of Transfer Event Master Mode Fault Event Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). ...

Page 103

... CKM f /4 CKM f /8 CKM f /16 CKM f /32 CKM f /64 CKM SPI Control-Status Register (SPI_STATUS_CR) Configuration Register 21 (015h) Read/Write Reset Value: 0000 0000 (00h) 7 SPIF WCOL OR ST52F510/F513/F514 SPR2 SPR1 SPR0 MODF - ...

Page 104

... ST52F510/F513/F514 Bit 7: SPIF Serial Peripheral data transfer flag. (read only) This bit is set by hardware when a transfer has been completed. generated if SPIE=1 in the SPI_CR register cleared by a software sequence (an access to the SPI_STATUS_CR register followed by a read or write to the SPI_IN/ SPI_OUT registers). ...

Page 105

... SPIDO7-SPIDO0 Data to be transmitted. The SPI_OUT register is used to transmit data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Warning: A write to the SPI_OUT register places data directly into the shift register for transmission. 0 ST52F510/F513/F514 105/106 ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...