mcf51cn128 Freescale Semiconductor, Inc, mcf51cn128 Datasheet

mcf51cn128

Manufacturer Part Number

mcf51cn128

Description

Mcf51cn128 Coldfire Microcontroller Cover Mcf51cn128

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCF51CN128.pdf (48 pages)

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Freescale Semiconductor

Data Sheet: Technical Data

MCF51CN128 ColdFire

Microcontroller

Cover: MCF51CN128

The MCF51CN128 device is a low-cost, low-power,

high-performance 32-bit ColdFire V1 microcontroller (MCU)

featuring 10/100 BASE-T/TX fast ethernet controller (FEC),

media independent interface (MII) to connect an external

physical transceiver (PHY), and multi-function external bus

interface.

MCF51CN128 also has multiple communication interfaces

for various ethernet gateway applications. MCF51CN128 is

the first ColdFire V1 device to incorporate ethernet and

external bus interface along with new features to minimize

power consumption and increase functionality in low-power

modes.

The MCF51CN128 features the following functional units:

• 32-bit ColdFire V1 Central Processing Unit (CPU)

• On-Chip Memory

• Ethernet

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up

– Provides 0.94 Dhrystone 2.1 MIPS per MHz

– ColdFire Instruction Set Revision C (ISA_C)

– Support for up to 45 peripheral interrupt requests and 7

– 128 KB Flash, 24 KB RAM

– Flash read/program/erase over full operating voltage

– On-chip memory aliased to create a contiguous memory

– Security circuitry to prevent unauthorized access to

– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet

to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz

CPU from 2.1 V to 1.8 V across temperature range of

–40 °C to 85 °C

performance when running from internal RAM

(0.76 DMIPS/MHz from flash)

software interrupts

and temperature

space with off-chip memory

Peripherals, RAM, and flash contents

controller with direct memory access (DMA); supports

half or full duplex; operation is limited to 3.0 V to 3.6 V

• External Bus

• Power-Saving Modes

• Clock Source Options

– MII—media independent interface to connect ethernet

– Mini-FlexBus—Multi-function external bus interface;

– Programmable options: access time per chip select, burst

– Two low-power stop modes, one of which allows limited

– Reduced-power wait mode shuts off CPU and allows

– Low-power run and wait modes allow peripherals to run

– Peripheral clock enable register can disable clocks to

– Low-power external oscillator that can be used in stop3

– Low-power real-time counter for use in run, wait, and

– 6 μs typical wake-up time from stop3 mode

– Pins and clocks to peripherals not available in smaller

– Oscillator (XOSC) — Loop-control pierce oscillator;

– Multi-Purpose Clock Generator (MCG) — Flexible

controller to external PHY; includes output clock for

external PHY

supports up to 1 MB memories, gate-array logic, simple

slave device or glueless interfaces to standard

chip-selected asynchronous memories

and burst-inhibited transfers per chip select, transfer

direction, and address setup and hold times

use of some peripherals (ADC, KBI, RTC)

full use of all peripherals; FEC can remain active and

conduct DMA transfers to RAM and assert an interrupt

to wake up the CPU upon completion

while the voltage regulator is in standby

unused modules, thereby reducing currents

mode to provide accurate clock source to active

peripherals

stop modes with internal and external clock sources

packages are automatically disabled for reduced current

consumption; no user interaction is needed

crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 25 MHz

clock source module with either frequency-locked-loop

(FLL) or phase-lock loop (PLL) clock options. FLL can

be controlled by internal or external reference and

MCF51CN128

48 QFN

7 mm × 7 mm

Document Number: MCF51CN128

80 LQFP

14 mm × 14 mm

Rev. 4, 5/2009

64 LQFP

10 mm × 10 mm

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